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1995 IEEE International SOI Conference Proceedings最新文献

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Universal mobility behavior in Si/SOI inversion layers and mobility degradation in extremely thin Si/SOI Si/SOI逆温层中的普遍迁移率行为和极薄Si/SOI中的迁移率退化
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526484
M. Shoji, Y. Omura, M. Tomizawa
{"title":"Universal mobility behavior in Si/SOI inversion layers and mobility degradation in extremely thin Si/SOI","authors":"M. Shoji, Y. Omura, M. Tomizawa","doi":"10.1109/SOI.1995.526484","DOIUrl":"https://doi.org/10.1109/SOI.1995.526484","url":null,"abstract":"This paper shows the physical origin and the limitation of the universal behavior of the effective mobility as a function of effective vertical electric field for fully depleted MOSFETs/SOI by investigating the electronic states of the inversion layers. In this context, the mobility degradation of extremely thin Si/SOI is also discussed.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131542834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Bandgap engineering technology for suppressing the substrate-floating-effect in 0.15 /spl mu/m SOI-MOSFETs 抑制0.15 /spl mu/m soi - mosfet衬底浮子效应的带隙工程技术
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526470
M. Yoshimi, A. Nishiyama, M. Terauchi, O. Arisumi, A. Murakoshi, Y. Ushiku, S. Takeno, K. Suzuki
{"title":"Bandgap engineering technology for suppressing the substrate-floating-effect in 0.15 /spl mu/m SOI-MOSFETs","authors":"M. Yoshimi, A. Nishiyama, M. Terauchi, O. Arisumi, A. Murakoshi, Y. Ushiku, S. Takeno, K. Suzuki","doi":"10.1109/SOI.1995.526470","DOIUrl":"https://doi.org/10.1109/SOI.1995.526470","url":null,"abstract":"The substrate floating effect is the most fundamental problem in SOI-MOSFETs. Conventional countermeasures, such as body-contact, LDD structure are accompanied by area penalty, Id degradation and other drawbacks. To suppress this effect, we have proposed the bandgap engineering method, in which a narrow bandgap material is formed in the source region. In this paper, an ideal structure for the bandgap engineering is discussed and actually achievable performance is estimated based on simulations and experiments for 0.15 /spl mu/m SOI-MOSFETs.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134503493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Simulation of the effects of manufacturing process variations on the characteristics of SOI MOSFETs 制造工艺变化对SOI mosfet特性影响的模拟
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526442
T. Sanders, M. J. Phelps
{"title":"Simulation of the effects of manufacturing process variations on the characteristics of SOI MOSFETs","authors":"T. Sanders, M. J. Phelps","doi":"10.1109/SOI.1995.526442","DOIUrl":"https://doi.org/10.1109/SOI.1995.526442","url":null,"abstract":"Successful scaling of SOI MOSFETs to deep sub-micron features for use in high density and low power applications will require a thorough understanding of the effect of process variation on device yield. Manufacturing steps that contribute most to device parameter variation must be identified so that tolerances can be tightened. This paper shows that Design of Experiments (DoE) methodology can be applied to commercial process and device simulation packages to gain insight into the process flow of SOI devices and to identify possible challenges to be met in the fabrication of future devices.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132814294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Role of the bipolar transistor on the hot-carrier-degradation of SOI MOSFETs 双极晶体管对SOI mosfet热载流子退化的影响
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526473
Y.S. Chang, S. Cristoloveanu, G. Reichert, P. Gentil, S.S. Li, J. Fossum
{"title":"Role of the bipolar transistor on the hot-carrier-degradation of SOI MOSFETs","authors":"Y.S. Chang, S. Cristoloveanu, G. Reichert, P. Gentil, S.S. Li, J. Fossum","doi":"10.1109/SOI.1995.526473","DOIUrl":"https://doi.org/10.1109/SOI.1995.526473","url":null,"abstract":"Hot-carrier-induced degradation is a major challenge for shrinking further the size of bulk Si or SOI components. Although there is no evidence that the aging of SOI MOSFETs is more severe than that of bulk Si counterparts, the degradation mechanisms are more complex: (i) not only the front gate but also the buried oxide and related interface may be damaged, (ii) interface coupling allows the front channel to sense the presence of defects at the opposite interface, (iii) the fields are different, and (iv) floating-body effects may come into play. The purpose of this work is to investigate the latter aspect by revealing the main consequences of stresses conducted in floating- and biased-body modes.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115485475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Radiation characterization of a low power 0.5 /spl mu/m SOI-CMOS technology 低功耗0.5 /spl mu/m SOI-CMOS技术的辐射特性
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526455
T.O. Vu, A. Nguyen, J. Cable
{"title":"Radiation characterization of a low power 0.5 /spl mu/m SOI-CMOS technology","authors":"T.O. Vu, A. Nguyen, J. Cable","doi":"10.1109/SOI.1995.526455","DOIUrl":"https://doi.org/10.1109/SOI.1995.526455","url":null,"abstract":"SOI technologies such as bonded and SIMOX are good candidates to replace SOS in environments requiring radiation hardness up to and above 1 Mrad. We have developed a 0.5 /spl mu/m SOI-CMOS process that is rad-hard to at least 300Krad(SiO2). The process and device characteristics, along with radiation results, are presented.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123569456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An analysis of buried-oxide growth in low-dose SIMOX wafers by high-temperature thermal oxidation 高温热氧化法对低剂量SIMOX硅片埋地氧化生长的影响
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526506
S. Masui, K. Kawamura, I. Hamaguchi, T. Yano, T. Nakajima, M. Tachimori
{"title":"An analysis of buried-oxide growth in low-dose SIMOX wafers by high-temperature thermal oxidation","authors":"S. Masui, K. Kawamura, I. Hamaguchi, T. Yano, T. Nakajima, M. Tachimori","doi":"10.1109/SOI.1995.526506","DOIUrl":"https://doi.org/10.1109/SOI.1995.526506","url":null,"abstract":"The buried-oxide (BOX) growth by a high-temperature thermal oxidation of low-dose SIMOX wafers is becoming an indispensable technique for the improvement of material quality, for example, surface roughness and BOX leak path density, as well as the slight decrease in the parasitic capacitance. The physical mechanism of the BOX growth by a thermal oxidation has been investigated for bonded wafers oxidized at 1100/spl deg/C; however, the typical oxidation temperature for low-dose SIMOX wafers is much higher than 1100/spl deg/C. To clarify the oxidation mechanism at higher temperatures and predict the thermally-grown BOX thickness for various conditions, we explore the oxidation process with a simple model based on Deal and Grove's analysis.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127584387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Transient effects in floating body SOI NMOSFETs 浮体SOI nmosfet的瞬态效应
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526486
J. Gautier, K. Jenkins, J. Sun
{"title":"Transient effects in floating body SOI NMOSFETs","authors":"J. Gautier, K. Jenkins, J. Sun","doi":"10.1109/SOI.1995.526486","DOIUrl":"https://doi.org/10.1109/SOI.1995.526486","url":null,"abstract":"The consequence of floating body operation of SOI devices is the existence of several phenomena, like the kink effect and supra ideal subthreshold slope. In this paper, we report the associated transient effects observed for fast gate pulses by high speed measurements and 2-D numerical simulations. It is shown that due to floating body operation, the drain current of SOI devices during fast switching is very different from the DC value. This must be taken into account for accurate simulation of circuits.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114534111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A comparative study of non-linearities in bulk and SOI linear resistors based on 2- and 4-transistor structures 基于2晶体管和4晶体管结构的体电阻和SOI线性电阻非线性的比较研究
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526462
B. Gentinne, V. Dessard, S. Louveaux, D. Flandre, J. Colinge
{"title":"A comparative study of non-linearities in bulk and SOI linear resistors based on 2- and 4-transistor structures","authors":"B. Gentinne, V. Dessard, S. Louveaux, D. Flandre, J. Colinge","doi":"10.1109/SOI.1995.526462","DOIUrl":"https://doi.org/10.1109/SOI.1995.526462","url":null,"abstract":"Both measurements and simulations based on accurate current models prove that the use of a SOI 4-transistor balanced structure as a passive triode resistor for continuous time MOSFET-C filters or integrators can give a linearity improvement of up to 20 dB over bulk counterparts.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129294713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Fully depleted dual-gated thin-film SOI p-MOSFET with an isolated buried polysilicon backgate 具有隔离埋式多晶硅后门的完全耗尽双栅极薄膜SOI p-MOSFET
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526497
J. Denton, G. Neudeck
{"title":"Fully depleted dual-gated thin-film SOI p-MOSFET with an isolated buried polysilicon backgate","authors":"J. Denton, G. Neudeck","doi":"10.1109/SOI.1995.526497","DOIUrl":"https://doi.org/10.1109/SOI.1995.526497","url":null,"abstract":"A p-channel Dual-Gated Thin-Film Silicon-on-insulator (DG-TFSOI) MOSFET has been fabricated with an isolated buried polysilicon backgate and is in a SOI island. This structure allows individual operation of each backgate of each device, rather than the present common backgate (substrate) structure. The ability to use a individual buried gate to dynamically shift the threshold voltage of each individual top MOSFET may have significant implications for low power circuits and offers a way to boost drive currents for faster switching. By using Epitaxial Lateral Overgrowth (ELO) the bottom thermal buried oxide can be specified to any thickness.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123026085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A physical thermal resistance model for vertical BJTs on SOI SOI上垂直bjt的物理热阻模型
1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI: 10.1109/SOI.1995.526472
D. T. Zweidinger, J. Brodsky, R. Fox
{"title":"A physical thermal resistance model for vertical BJTs on SOI","authors":"D. T. Zweidinger, J. Brodsky, R. Fox","doi":"10.1109/SOI.1995.526472","DOIUrl":"https://doi.org/10.1109/SOI.1995.526472","url":null,"abstract":"Because BJT currents are highly temperature sensitive, self-heating is very important in analog BJT circuits. Dielectrically isolated BJTs (DIBJTs) typically have thermal resistance R/sub TH/ three or more times higher than their bulk counterparts. Circuit simulators are readily modified to account for such effects, but characterizing thermal effects in DIBJTs is rather difficult: self-heating complicates extraction of the temperature dependences and R/sub TH/, and models that predict R/sub TH/ in bulk BJTs do not apply for SOI because of the more complicated boundary conditions. This paper describes a scalable model for R/sub TH/ in vertical DIBJTs, along with a technique for extracting R/sub TH/ in BJTs. The modeled measurements are shown to agree quite well.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127924446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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