Simulation of the effects of manufacturing process variations on the characteristics of SOI MOSFETs

Abstract

Successful scaling of SOI MOSFETs to deep sub-micron features for use in high density and low power applications will require a thorough understanding of the effect of process variation on device yield. Manufacturing steps that contribute most to device parameter variation must be identified so that tolerances can be tightened. This paper shows that Design of Experiments (DoE) methodology can be applied to commercial process and device simulation packages to gain insight into the process flow of SOI devices and to identify possible challenges to be met in the fabrication of future devices.