Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)最新文献

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Spin-on dielectric stack low-k integration with EB curing technology for 45nm-node and beyond 45纳米及以上节点的自旋介电堆低k集成与EB固化技术
H. Nagai, K. Maekawa, M. Iwashita, M. Muramatsu, K. Kubota, K. Hinata, T. Kokubo, A. Shiota, M. Hattori, H. Nagano, K. Tokushige, M. Kodera, K. Mishima
{"title":"Spin-on dielectric stack low-k integration with EB curing technology for 45nm-node and beyond","authors":"H. Nagai, K. Maekawa, M. Iwashita, M. Muramatsu, K. Kubota, K. Hinata, T. Kokubo, A. Shiota, M. Hattori, H. Nagano, K. Tokushige, M. Kodera, K. Mishima","doi":"10.1109/IITC.2004.1345721","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345721","url":null,"abstract":"To achieve effective k value less than 3.0, we investigated spin-on dielectric stack damascene integration scheme with electron beam (EM) cure. By using porous-MSQ (k=2.3) as ILD and dense-MSQ (k=2.9) as hard mask (HM), effective k value could be lowered, and by EB curing the full dielectric stack only once, mechanical strength for both ILD and HM were improved and a reduced thermal budget was obtained. In addition, a low damage resist strip process for the low-k materials was evaluated. These elements of BEOL technology have applicability to 45nm technology node and beyond.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125296645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High speed Si-based optical modulator for on-chip optical interconnects 用于片上光互连的高速硅基光调制器
D. Marris, A. Lupu, D. Pascal, J. Cercus, L. Vivien, E. Cassan, S. Laval
{"title":"High speed Si-based optical modulator for on-chip optical interconnects","authors":"D. Marris, A. Lupu, D. Pascal, J. Cercus, L. Vivien, E. Cassan, S. Laval","doi":"10.1109/IITC.2004.1345712","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345712","url":null,"abstract":"A modulation-doped SiGe-Si multiple quantum well modulator (MD-MQW) embedded in a reverse biased PIN junction is described. Experimental and theoretical results show that the optical index variation can be achieved by plasma-dispersion effect associated to carrier depletion. Interferometric integrated structures proper to transform the obtained phase modulation into amplitude modulation are presented, and the main properties of the optical modulator are evaluated, including intrinsic rapidity, contrast ratio and insertion losses.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130102331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
X-ray and neutron porosimetry as powerful methodologies for determining structural characteristics of porous low-k thin films x射线和中子孔隙度测定法是测定多孔低钾薄膜结构特征的有力方法
Hae-Jeong Lee, B. Vogt, C. Soles, Da-Wei Liu, B. Bauer, Wen-Li Wu, E. Lin, Gwi-Gwon Kang, M. Ko
{"title":"X-ray and neutron porosimetry as powerful methodologies for determining structural characteristics of porous low-k thin films","authors":"Hae-Jeong Lee, B. Vogt, C. Soles, Da-Wei Liu, B. Bauer, Wen-Li Wu, E. Lin, Gwi-Gwon Kang, M. Ko","doi":"10.1109/IITC.2004.1345718","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345718","url":null,"abstract":"Methylsilsesquioxane based porous low-k dielectric films with varying porogen loading have been characterized using X-ray and neuron porosimetry to determine their pore size distribution, average density, wall density, porosity, density profiles, and porosity profiles. The porosity and the average pore size of the sample with 45% porogen were 52% and 23 /spl Aring/ in radius, respectively. Pore size, was consistent with that from small angle neutron scattering measurements. The wall density was found to be independent of the porogen content and it appeared that the porogen was 100% effective in generating pores.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133277663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Electrochemically induced defects during post Cu CMP cleaning Cu CMP后清洗过程中电化学诱导缺陷
W. Chiou, Y.H. Chen, S.N. Lee, S. Jeng, S. Jang, M. Liang
{"title":"Electrochemically induced defects during post Cu CMP cleaning","authors":"W. Chiou, Y.H. Chen, S.N. Lee, S. Jeng, S. Jang, M. Liang","doi":"10.1109/IITC.2004.1345715","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345715","url":null,"abstract":"The electrochemical properties of various cleaning reagents of high, medium or low pH values for post Cu CMP cleaning and their interaction mechanisms with Cu surfaces were studied. Results showed that for the Cu in TMAH (pH=11) a reverse reaction, Cu re-deposition, was also observed although the Cu was easier to corrode due to its more negative corrosion potential in this solution. Because of this abnormal Cu re-deposition, Cu anode and cathode reactions were found to occur at the same Cu islands, where the Cu were corroded and then re-filled by re-deposition to form allow defects. These defects were extremely difficult to detect by in-line defect inspection tools during wafer processing and can only be identified by FA after WAT failures. Careful examinations of electrochemical properties revealed that hump in the I-V curve is the key to this abnormalities and a novel solution was proposed and developed to eliminate these defects.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121775839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Quantitative control of plasma-surface interactions for highly reliable interconnects 用于高可靠互连的等离子体表面相互作用的定量控制
K. Yatsuda, T. Tatsumi, K. Kawahara, Y. Enomoto, T. Hasegawa, K. Hanada, T. Saito, Y. Morita, K. Shinohara, T. Yamane
{"title":"Quantitative control of plasma-surface interactions for highly reliable interconnects","authors":"K. Yatsuda, T. Tatsumi, K. Kawahara, Y. Enomoto, T. Hasegawa, K. Hanada, T. Saito, Y. Morita, K. Shinohara, T. Yamane","doi":"10.1109/IITC.2004.1345698","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345698","url":null,"abstract":"Plasma technologies for highly reliable Cu/low-k interconnects were developed. Although good dual damascene profiles were fabricated, insufficiently optimized plasma for etching (and/or ashing) degraded Cu and SiOCH surface, and corrupted the interface between Cu and barrier metal (BM) after all. Therefore, we clarified the effect of degradation in the interconnect reliabilities, and controlled the densities of reactive species (CFx and O) in the plasma to optimize the reactions between plasma and material surfaces. Consequently, we achieved high yield and high reliability for 90-nm-node Cu/low-k interconnects in over 40 lots.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124880387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The application of simultaneous ebeam cure methods for 65 nm node Cu/low-k technology with hybrid (PAE/MSX) structure 同步电子束固化方法在混合(PAE/MSX)结构65 nm节点Cu/低k技术中的应用
H. Miyajima, K. Fujita, R. Nakata, T. Yoda, N. Hayasaka
{"title":"The application of simultaneous ebeam cure methods for 65 nm node Cu/low-k technology with hybrid (PAE/MSX) structure","authors":"H. Miyajima, K. Fujita, R. Nakata, T. Yoda, N. Hayasaka","doi":"10.1109/IITC.2004.1345754","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345754","url":null,"abstract":"High performance low-k hybrid-DD structure (poly-arylene-ether (PAE)/ poly-methylsiloxane (MSX)) is realized by simultaneous electron beam (ebeam) curing technique, and applied to a 65 nm node Cu/low-k multilevel damascene process. By eBeam curing for MSX, while maintaining a k value, both mechanical strength and adhesion strength of the bottom interface have been improved. In addition, since the introduction of the ebeam cure technique reduces cure temperature and time of spin on dielectric formation, the thermal budget is dramatically reduced. The simultaneous ebeam curing of PAE/MSX hybrid structure realizes low-cost and high reliability Cu/low-k interconnects. It is also considered that this ebeam cure technology will be very effective in 65 nm node devices and beyond.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122688596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Carbon nanotube vias for future LSI interconnects 未来大规模集成电路互连的碳纳米管通孔
M. Nihei, M. Horibe, A. Kawabata, Y. Awano
{"title":"Carbon nanotube vias for future LSI interconnects","authors":"M. Nihei, M. Horibe, A. Kawabata, Y. Awano","doi":"10.1109/IITC.2004.1345767","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345767","url":null,"abstract":"We have developed carbon nanotube (CNT) vias consisting of about 1000 tubes. The total resistance of the CNT via was measured as three orders of magnitude lower than the current flows in parallel through about 1000 tubes. There is no degradation observed for 100 hours at the via current density of 2/spl times/10/sup 6/ A/cm/sup 2/, which is favourably with Cu vias. This is the first trial demonstration of CNT vias for future LSI interconnects.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"176 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132566185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 61
A technique for incorporation of a heatsink for a system utilizing integrated circuits with wireless connections to an off-chip antenna 一种为利用集成电路与片外天线无线连接的系统集成散热片的技术
Ran Li, Xiaoling Guo, K. O
{"title":"A technique for incorporation of a heatsink for a system utilizing integrated circuits with wireless connections to an off-chip antenna","authors":"Ran Li, Xiaoling Guo, K. O","doi":"10.1109/IITC.2004.1345726","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345726","url":null,"abstract":"Using fins and apertures (7 mm /spl times/ 1.5 mm) opened in a base-plate of a commercially available heatsink as waveguides, a wireless clock distribution system using an external antenna can be made to work at 24 GHz in the presence of a heatsink. Surprisingly, the presence of heatsink improves power transmission gain by 1-5 dB. The measurements indicate that the receiving antenna size could be reduced to 0.2 mm or less for clock distribution systems using an external antenna.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132149482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Effects of dielectric liners on TDDB lifetime of a Cu/ low-k interconnect 介质衬垫对Cu/低k互连TDDB寿命的影响
T. Tsui, P. Matz, R. Willecke, E. Zielinski, Tae Kim, G. Haase, J. McPherson, A. Singh, A. Mckerrow
{"title":"Effects of dielectric liners on TDDB lifetime of a Cu/ low-k interconnect","authors":"T. Tsui, P. Matz, R. Willecke, E. Zielinski, Tae Kim, G. Haase, J. McPherson, A. Singh, A. Mckerrow","doi":"10.1109/IITC.2004.1345692","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345692","url":null,"abstract":"Thin films of silicon nitride (SiN) or silicon carbonitride (SiCN) were deposited as liners at metal-1 in a dual level metal Cu/organosilicate glass interconnect. Breakdown field and time dependent dielectric breakdown lifetime testing of comb/serpent test structures with SiN or SiCN liners showed improvements in performance, relative to a baseline no liner split. Two dimensional electric field simulations demonstrated that the dielectric liner significantly reduced the electric field at the Cu/OSG/etch stop interface.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"21 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131614594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High reliability Cu interconnection utilizing a low contamination CoWP capping layer 采用低污染cop封盖层的高可靠性铜互连
T. Ishigami, T. Kurokawa, Y. Kakuhara, B. Withers, J. Jacobs, A. Kolics, I. Ivanov, M. Sekine, K. Ueno
{"title":"High reliability Cu interconnection utilizing a low contamination CoWP capping layer","authors":"T. Ishigami, T. Kurokawa, Y. Kakuhara, B. Withers, J. Jacobs, A. Kolics, I. Ivanov, M. Sekine, K. Ueno","doi":"10.1109/IITC.2004.1345691","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345691","url":null,"abstract":"Copper (Cu) damascene interconnects with a cobalt tungsten phosphorus (CoWP) capping layer were developed using an alkaline-metal-free electrodes plating process without palladium (Pd) catalyst activation. The wafer contamination level after processing is consistent with requirements for present LSI fabrication lines. Within wafer CoWP deposition uniformity is high and interconnects wire resistance increases by less than 5% after deposition. Electromigration (EM) testing shows no failures after two thousand hours and stress induced voiding (SIV) testing shows no failure after three thousand hours. This EM result is a 2 order or magnitude improvement over a non CoWP process.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116957939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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