International Conference on Embedded Software最新文献_第8页

Towards a time-triggered schedule calculation tool to support model-based embedded software design 向着一个支持基于模型的嵌入式软件设计的时间触发调度计算工具的方向发展

International Conference on Embedded Software Pub Date : 2009-10-12 DOI: 10.1145/1629335.1629358

Joseph Porter, G. Karsai, J. Sztipanovits

{"title":"Towards a time-triggered schedule calculation tool to support model-based embedded software design","authors":"Joseph Porter, G. Karsai, J. Sztipanovits","doi":"10.1145/1629335.1629358","DOIUrl":"https://doi.org/10.1145/1629335.1629358","url":null,"abstract":"Time-triggered architectures (TTA) provide replica determinism in safety-critical distributed embedded software designs. TTA has become a crucial part of many high-confidence embedded paradigms, as it decouples functional concerns from platform timing concerns in system designs. Complex embedded software development workflows for safety-critical applications are increasingly managed by model-based design tools, in order to support automated verification and reconcile conflicts between functional and non-functional concerns in designs. We present a prototype scheduling tool (ESched) which calculates cyclic schedules for time-triggered networks. ESched supports the model-based workflow of the ESMoL modeling language and tool suite. Using ESMoL, designers can rapidly iterate through simulating a control design, capturing platform effects in models, generating a schedule (if feasible), and re-simulating the control design subject to the platform model and the computed schedule. ESched specifications include a number of useful platform parameters, and it supports troubleshooting of infeasible schedules by allowing the user to specify partial platform models to solve.","PeriodicalId":143573,"journal":{"name":"International Conference on Embedded Software","volume":"46 41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128866567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Symbolic state traversal for WCET analysis WCET分析的符号状态遍历

International Conference on Embedded Software Pub Date : 2009-10-12 DOI: 10.1145/1629335.1629354

Stephan Wilhelm, Björn Wachter

引用次数: 21

Compositional verification of fault-tolerant real-time programs 容错实时程序的组成验证

International Conference on Embedded Software Pub Date : 2009-10-12 DOI: 10.1145/1629335.1629341

Borzoo Bonakdarpour, S. Kulkarni

引用次数: 4

Modal interfaces: unifying interface automata and modal specifications 模态接口:统一接口自动机和模态规范

International Conference on Embedded Software Pub Date : 2009-10-12 DOI: 10.1145/1629335.1629348

Jean-Baptiste Raclet, Éric Badouel, A. Benveniste, B. Caillaud, Axel Legay, R. Passerone

{"title":"Modal interfaces: unifying interface automata and modal specifications","authors":"Jean-Baptiste Raclet, Éric Badouel, A. Benveniste, B. Caillaud, Axel Legay, R. Passerone","doi":"10.1145/1629335.1629348","DOIUrl":"https://doi.org/10.1145/1629335.1629348","url":null,"abstract":"This paper presents a unification of interface automata and modal specifications, two radically dissimilar models for interface theories. Interface automata is a game-based model, which allows to make assumptions on the environment and propose an optimistic view for composition : two components can be composed if there is an environment where they can work together. Modal specification is a language theoretic account of a fragment of the modal mu-calculus logic that is more complete but which does not allow to distinguish between the environment and the component. Partial unifications of these two frameworks have been explored recently. A first attempt by Larsen et al. considers modal interfaces, an extension of modal specifications that deals with compatibility issues in the composition operator. However, this composition operator is incorrect. A second attempt by Raclet et al. gives a different perspective, and emphasises on conjunction and residuation of modal specifications, including when interfaces have dissimilar alphabets, but disregards interface compatibility. The present paper contributes a thorougher unification of the two theories by correcting the modal interface composition operator presented in the paper by Larsen et al., drawing a complete picture of the modal interface algebra, and pushing even further the comparison between interface automata, modal automata and modal interfaces.","PeriodicalId":143573,"journal":{"name":"International Conference on Embedded Software","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117162090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 78

Cache-aware scheduling and analysis for multicores 多核的缓存感知调度和分析

International Conference on Embedded Software Pub Date : 2009-10-12 DOI: 10.1145/1629335.1629369

Nan Guan, Martin Stigge, W. Yi, Ge Yu

{"title":"Cache-aware scheduling and analysis for multicores","authors":"Nan Guan, Martin Stigge, W. Yi, Ge Yu","doi":"10.1145/1629335.1629369","DOIUrl":"https://doi.org/10.1145/1629335.1629369","url":null,"abstract":"The major obstacle to use multicores for real-time applications is that we may not predict and provide any guarantee on real-time properties of embedded software on such platforms; the way of handling the on-chip shared resources such as L2 cache may have a significant impact on the timing predictability. In this paper, we propose to use cache space isolation techniques to avoid cache contention for hard real-time tasks running on multicores with shared caches. We present a scheduling strategy for real-time tasks with both timing and cache space constraints, which allows each task to use a fixed number of cache partitions, and makes sure that at any time a cache partition is occupied by at most one running task. In this way, the cache spaces of tasks are isolated at run-time.\u0000 As technical contributions, we have developed a sufficient schedulability test for non-preemptive fixed-priority scheduling for multicores with shared L2 cache, encoded as a linear programming problem. To improve the scalability of the test, we then present our second schedulability test of quadratic complexity, which is an over approximation of the first test. To evaluate the performance and scalability of our techniques, we use randomly generated task sets. Our experiments show that the first test which employs an LP solver can easily handle task sets with thousands of tasks in minutes using a desktop computer. It is also shown that the second test is comparable with the first one in terms of precision, but scales much better due to its low complexity, and is therefore a good candidate for efficient schedulability tests in the design loop for embedded systems or as an on-line test for admission control.","PeriodicalId":143573,"journal":{"name":"International Conference on Embedded Software","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122134518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 140

SyncCharts in C: a proposal for light-weight, deterministic concurrency C中的SyncCharts:轻量级、确定性并发的建议

International Conference on Embedded Software Pub Date : 2009-10-12 DOI: 10.1145/1629335.1629366

R. V. Hanxleden

引用次数: 43

Tax-and-spend: democratic scheduling for real-time garbage collection 税收和支出:实时垃圾收集的民主调度

International Conference on Embedded Software Pub Date : 2008-10-19 DOI: 10.1145/1450058.1450092

Joshua S. Auerbach, D. F. Bacon, P. Cheng, D. Grove, Ben Biron, Charlie Gracie, Bill McCloskey, Aleksandar Micic, Ryan Sciampacone

{"title":"Tax-and-spend: democratic scheduling for real-time garbage collection","authors":"Joshua S. Auerbach, D. F. Bacon, P. Cheng, D. Grove, Ben Biron, Charlie Gracie, Bill McCloskey, Aleksandar Micic, Ryan Sciampacone","doi":"10.1145/1450058.1450092","DOIUrl":"https://doi.org/10.1145/1450058.1450092","url":null,"abstract":"Real-time Garbage Collection (RTGC) has recently advanced to the point where it is being used in production for financial trading, military command-and-control, and telecommunications. However, among potential users of RTGC, there is enormous diversity in both application requirements and deployment environments.\u0000 Previously described RTGCs tend to work well in a narrow band of possible environments, leading to fragile systems and limiting adoption of real-time garbage collection technology.\u0000 This paper introduces a collector scheduling methodology called tax-and-spend and the collector design revisions needed to support it. Tax-and-spend provides a general mechanism which works well across a variety of application, machine, and operating system configurations. Tax-and-spend subsumes the predominant pre-existing RTGC scheduling techniques. It allows different policies to be applied in different contexts depending on the needs of the application. Virtual machines can co-exist compositionally on a single machine.\u0000 We describe the implementation of our system, Metronome-TS, as an extension of the Metronome collector in IBM's Real-time J9 virtual machine product, and we evaluate it running on an 8-way SMP blade with a real-time Linux kernel. Compared to the state-of-the-art Metronome system on which it is based, implemented in the identical infrastructure, it achieves almost 3x shorter latencies, comparable utilization at a 2.5x shorter time window, and mean throughput improvements of 10-20%.","PeriodicalId":143573,"journal":{"name":"International Conference on Embedded Software","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132943848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 37

DBS4video: dynamic luminance backlight scaling based on multi-histogram frame characterization for video streaming application DBS4video:基于多直方图帧表征的动态亮度背光缩放视频流应用

International Conference on Embedded Software Pub Date : 2008-10-19 DOI: 10.1145/1450058.1450074

M. Ruggiero, Andrea Bartolini, L. Benini

{"title":"DBS4video: dynamic luminance backlight scaling based on multi-histogram frame characterization for video streaming application","authors":"M. Ruggiero, Andrea Bartolini, L. Benini","doi":"10.1145/1450058.1450074","DOIUrl":"https://doi.org/10.1145/1450058.1450074","url":null,"abstract":"Almost every modern portable handheld device is equipped with a coloured LCD display. The backlight of the LCD accounts for a significant percentage of the total energy consumption. Substantial energy savings can be achieved by dynamically adapting backlight intensity levels on such low-power portable devices. In this paper, we present the DBS4video framework which allows dynamic scaling of the backlight with a negligible impact on QoS for video streaming applications. DBS4video exploits in a smart and efficient way the hardware image processing unit integrated in almost every new multimedia application processor to implement a hardware assisted image compensation. The proposed approach overcomes CPU-intensive techniques by saving system power without requiring either a dedicated display technology or hardware modification. We introduce also a new image processing kernel based on multiple histograms collection for a single frame. We provide a real implementation of the proposed framework on a Freescale application development board based on the i.MX31 processor. We carried out a full characterization of the overall system power consumption versus QoS.","PeriodicalId":143573,"journal":{"name":"International Conference on Embedded Software","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131399007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

State space abstraction for parameterized self-stabilizing embedded systems 参数化自稳定嵌入式系统的状态空间抽象

International Conference on Embedded Software Pub Date : 2008-10-19 DOI: 10.1145/1450058.1450061

N. Liveris, H. Zhou, R. Dick, P. Banerjee

引用次数: 10

LTFTL: lightweight time-shift flash translation layer for flash memory based embedded storage LTFTL:轻量级时移闪存转换层，用于基于闪存的嵌入式存储

International Conference on Embedded Software Pub Date : 2008-10-19 DOI: 10.1145/1450058.1450066

Kyoungmoon Sun, Seungjae Baek, Jongmoo Choi, Donghee Lee, S. Noh, S. Min

{"title":"LTFTL: lightweight time-shift flash translation layer for flash memory based embedded storage","authors":"Kyoungmoon Sun, Seungjae Baek, Jongmoo Choi, Donghee Lee, S. Noh, S. Min","doi":"10.1145/1450058.1450066","DOIUrl":"https://doi.org/10.1145/1450058.1450066","url":null,"abstract":"Flash memory storage has been widely used in various embedded systems such as digital cameras, MP3 players, cellular phones, and DMB devices and now it applies to PCs as a form of SSDs. Characteristics of Flash memory necessitate a software layer called FTL (Flash Translation Layer) that directs modified data to new places in Flash memory and maintains a mapping between a logical sector number to a physical page. We notice that this out-of-place update scheme of the FTL allows a low-overhead time-shifting between multiple versions of storage state. From this observation, we propose LTFTL (Lightweight Time-shift FTL) that provides not only multiple versions of storage state but also an open-ended interface to traverse them. This open-ended interface can be used to support fault-resilience schemes, transactions of various granularities, and user-friendly roll-back services. Experimental results from a prototype implementation show that the proposed LTFTL can (1) provide a low-overhead time-shift capability at the user level by maintaining multiple storage states and (2) enhance the reliability/survivability of Flash memory by allowing to roll back to a previous consistent storage state at the storage system level.","PeriodicalId":143573,"journal":{"name":"International Conference on Embedded Software","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124780964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18