Towards a time-triggered schedule calculation tool to support model-based embedded software design

Joseph Porter, G. Karsai, J. Sztipanovits
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引用次数: 17

Abstract

Time-triggered architectures (TTA) provide replica determinism in safety-critical distributed embedded software designs. TTA has become a crucial part of many high-confidence embedded paradigms, as it decouples functional concerns from platform timing concerns in system designs. Complex embedded software development workflows for safety-critical applications are increasingly managed by model-based design tools, in order to support automated verification and reconcile conflicts between functional and non-functional concerns in designs. We present a prototype scheduling tool (ESched) which calculates cyclic schedules for time-triggered networks. ESched supports the model-based workflow of the ESMoL modeling language and tool suite. Using ESMoL, designers can rapidly iterate through simulating a control design, capturing platform effects in models, generating a schedule (if feasible), and re-simulating the control design subject to the platform model and the computed schedule. ESched specifications include a number of useful platform parameters, and it supports troubleshooting of infeasible schedules by allowing the user to specify partial platform models to solve.
向着一个支持基于模型的嵌入式软件设计的时间触发调度计算工具的方向发展
时间触发架构(TTA)为安全关键型分布式嵌入式软件设计提供了副本确定性。TTA已经成为许多高可信度嵌入式范例的关键部分,因为它将系统设计中的功能关注点与平台时序关注点解耦。安全关键应用程序的复杂嵌入式软件开发工作流越来越多地由基于模型的设计工具管理,以支持自动验证并协调设计中功能和非功能关注点之间的冲突。我们提出了一个计算时间触发网络循环调度的原型调度工具(ESched)。ESched支持ESMoL建模语言和工具套件的基于模型的工作流。使用ESMoL,设计人员可以快速迭代模拟控制设计,在模型中捕获平台效果,生成调度(如果可行),并根据平台模型和计算调度重新模拟控制设计。ESched规范包括许多有用的平台参数,并且通过允许用户指定要解决的部分平台模型,它支持对不可行的时间表进行故障排除。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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