1996 Proceedings 46th Electronic Components and Technology Conference最新文献

{"title":"Development of high conductivity lead (Pb)-free conducting adhesives","authors":"S.K. Kang, R. Rai, S. Purushothaman","doi":"10.1109/ECTC.1996.517444","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517444","url":null,"abstract":"Electrically conducting adhesive technology is one of the alternatives being actively investigated for the possibility of replacing the solder interconnection technology used for microelectronics applications. An isotropically conducting adhesive consists of metallic filler particles dispersed in the matrix of a polymer resin. Silver-filled epoxy resin is commonly used for thermal conduction in die attach applications. Silver particles can provide electrical and/or thermal conduction, while epoxy provides adhesive bonding of the components to a substrate. This material has several limitations when it is-considered as a replacement for solder interconnections, such as low electrical conductivity, low joint strength, increase in contact resistance upon thermal cycling, lack of reworkability, and silver migration. In order to overcome these limitations, a new formulation is proposed based on alternative Pb-free conducting filler powder and tailored polymer resins. The conducting filler particles are coated with low melting point, non-toxic metals which can be fused to achieve metallurgical bonding between adjacent particles as well as to a substrate. This new conductive adhesive material has shown improved electrical and mechanical properties over the existing silver-filled epoxy materials.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124128536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simultaneous switching noise simulation for thin film packages using macromodeling technique","authors":"C. Huang, M. Çelik, J. Prince","doi":"10.1109/ECTC.1996.550490","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550490","url":null,"abstract":"This paper presents a fast and accurate methodology for Simultaneous Switching Noise (SSN) simulation for thin film packaging structures using a macro-modeling technique. The combination of interconnect macromodels and SPICE simulation for nonlinear drivers make this technique attractive for large SSN simulation. This technique results in one order of magnitude improvement in the simulation speed for SSN when compared with conventional SPICE run time.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123672421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Embedded thin film resistors, capacitors and inductors in flexible polyimide films","authors":"T. Lenihan, L. Schaper, Y. Shi, G. Morcan, J. Parkerson","doi":"10.1109/ECTC.1996.517382","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517382","url":null,"abstract":"The High Density Electronics Center (HiDEC) at the University of Arkansas is working with the Sheldahl MCM-L Consortium and Rensselaer Polytechnic Institute (RPI) to develop low-cost embedded resistors, capacitors, and inductors in flexible polyimide films under an ARPA contract. Embedding thin-film passive devices into polyimide layers as part of a Multichip Module (MCM) system is new. The design concept allows fabrication and testing of embedded passive devices before assembling them into an MCM-L substrate. Embedded passive devices are needed as an enhancement to present day MCM-L and MCM-D technologies. The ability to remove devices such as terminating resistors and decoupling capacitors from the surfaces of PCB boards and MCMs into a flexible film, at low cost, would be a break-through for MCM technology. The devices are made into a flexible MCM package using a 2 layer interconnect system called the Interconnected Mesh Power System (IMPS) developed and patented at the University of Arkansas. The IMPS interconnection topology incorporates fine line lithography and batch via generation to allow planar power and ground distribution, and dense signal interconnection, on only two metal layers. The materials being used are NiCr, TaN, and CrSi for the resistors and Ta/sub x/O/sub y/ and BaTiO/sub x/ for the capacitors. Contacts, interconnecting signal lines, and power lines are made with Cu metallurgy. The devices are made on a 25 /spl mu/m or 50 /spl mu/m thick polyimide film and are encapsulated with the same polyimide.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125592855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characteristics of VCSEL arrays for parallel optical interconnects","authors":"M. Lebby, C. Gaw, Wenbin Jiang, P. Kiely, C. Shieh, P. Claisse, J. Ramdani, D. H. Hartman, D. Schwartz, J. Grula","doi":"10.1109/ECTC.1996.517404","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517404","url":null,"abstract":"The use of vertical cavity surface emitting lasers (VCSELs)in a parallel optical interconnect for Motorola's OPTOBUS/sup TM/ interconnect was made public over 1 year ago. This was the first time VCSELs were introduced into a product which took advantage of the excellent qualities of VCSELs over edge-emitting lasers. Motorola's OPTOBUS/sup TM/ interconnect is a ten channel parallel bi-directional data link based on two 10 channel multimode fiber ribbons. One of the key differences in this type of interconnect compared with previous data link designs is the use of the VCSELs as the optical source for the link's fiber optic transmitter. A single 1/spl times/10 VCSEL array from a GaAs wafer is die attached to a 10 channel GUIDECAST/sup TM/ optical interface unit which couples the emission from each laser device to its corresponding fiber ribbon channel and thus negates the use of expensive manufacturing techniques such as active alignment and pigtailing. The OPTOBUS/sup TM/ interconnect achieves its performance goals (which include low cost) via the unique characteristics of the GaAs VCSELs arrays. For example, the 850 nm devices produce a circular symmetric beam with a half angle of about 10 degrees allowing the coupling loss into the waveguide to be less than 3 dB. In addition, to maintain low manufacturing costs, each VCSEL array is individually and automatically probe tested (just as in the silicon industry) to verify that each VCSEL achieves the OPTOBUS/sup TM/ interconnect's stringent electrical, optical, thermal and mechanical specifications. Typical computer generated wafer maps from automated production tooling and statistical parametric results are discussed. The combination of low threshold currents with superior thermal and optical performance allow the devices to be modulated under fixed bias conditions. Typical drive currents of 3X threshold are used to obtain nominal FDA Class 1 safety optical power levels from the GUIDECAST/sup TM/ optical interface unit.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130539349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Practical considerations for the design, performance, and application of plastic BGA packages","authors":"T. Evans","doi":"10.1109/ECTC.1996.550511","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550511","url":null,"abstract":"As the number of available package types expand to include Plastic Ball Grid Array (PBGA), and performance limitations become more apparent, vast amounts of new information must be properly utilized to make the best design choices at a package level. PBGAs can theoretically satisfy many packaging requirements, but present themselves as a greater risk since they have not yet been thoroughly characterized. Specifically, new product development is jeopardized by integrated circuit performance that can be limited by PBGA, printed circuit board, and system level design, so a critical need is approaching for concurrent engineering design techniques and modeling tools. A design, performance, and application matrix is discussed and may be the first step in focusing these new methods of evaluation on PBGA package technology.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123093970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of stress singularity fields and stress intensity factors for interfacial delamination (an application of thermosetting polyimide for a tapeless lead-on-chip (LOC) package)","authors":"M. Amagai","doi":"10.1109/ECTC.1996.517421","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517421","url":null,"abstract":"The reliability of semiconductor devices and packages used in microelectronics is compromised by interfacial delamination and homogenous cracking that is initiated at the edge of the interface between dissimilar materials during processing and stress tests. These failures have certain characteristics in that they begin at the stress singularity point. The knowledge of interfacial fracture mechanics is very important to the design for reliability of these devices and packages. In this paper, a model of stress singularity is proposed and applications of the model for the characterization of interfaces are subsequently presented. Examples are integrated circuit (IC) device interfaces and plastic package interfaces. These interfaces were mainly characterized with the order of stress singularity. Furthermore, this study demonstrates applications of the stress intensity factors for the stress singularity fields. The stress intensity factors were obtained from a r-/spl theta/ coordinate system, the order of stress singularity, the Dunders' parameters, and the extrapolation as a function of distance. The relationship between the stress intensity factors and the interfacial fracture toughness strength as a function of mode mixity was also investigated for delamination at the edge of the interface. The proposed numerical scheme was verified by the experiments on the lead-on-chip (LOC) package delamination in a soldering process.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"46 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120904983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal and viscoelastic characterization of transfer-molded epoxy encapsulant during simulated post-mold cure","authors":"S. Chew","doi":"10.1109/ECTC.1996.550809","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550809","url":null,"abstract":"This paper describes the characterization of epoxy mold compound by subjecting transfer-molded encapsulants to a temperature programme simulating post-mold cure using thermomechanical analysis and dynamic mechanical analysis. The real-time change in dimension and viscoelastic properties of the epoxy encapsulant during an experimental post-mold cure process is measured. Results show evidence of residual cure shrinkage and flexural storage modulus growth occuring during experimental post-mold cure; sharp initially but stabilize subsequently. A minimum post-mold cure duration is recommended in order to ensure optimum dimensional and mechanical stability of the epoxy encapsulant.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130660799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Recipe synthesis for PECVD SiO/sub 2/ films using neural networks and genetic algorithms","authors":"Seung-Soo Han, G. May","doi":"10.1109/ECTC.1996.550508","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550508","url":null,"abstract":"Silicon dioxide films deposited by plasma-enhanced chemical vapor deposition PECVD) are useful as interlayer dielectrics for metal-insulator structures such as multichip modules. Due to the complex nature of particle dynamics within a plasma, it is difficult to determine the exact nature of the relationship between PECVD process conditions and their effects on critical output parameters. In this study, neural network process models are used in conjunction with genetic algorithms to determine the necessary process recipes to achieve novel film qualities. To characterize the PECVD process, SiO/sub 2/ films deposited in a plasma-Therm 700 series PECVD system under varying conditions are analyzed using a central composite experimental design. Parameters varied include substrate temperature, pressure, RF power, silane flow and nitrous oxide flow. Data from this experiment is used to train back-propagation neural networks to model deposition rate, refractive index, permittivity, film stress, wet etch rate, uniformity, silanol concentration, and water concentration. A recipe synthesis procedure is then performed using genetic algorithms, Powell's algorithm, the simplex method, and hybrid combinations thereof to generate the necessary deposition conditions to obtain novel film qualities, including zero residual stress, 0% non-uniformity, 0% impurities, and low permittivity. Recipes predicted by these techniques are verified by experiment, and the performance of each synthesis method is compared.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132931296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The packaging of large spot-size optoelectronic devices","authors":"J. Collins, I. Lealman, P.J. Fiddyment, A. Thurlow, C. Ford, D. Rogers, C.A. Jones","doi":"10.1109/ECTC.1996.517453","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517453","url":null,"abstract":"Lasers have been passively aligned to cleaved singlemode optical fibres on a silicon bench with coupling efficiencies of over 50%. This is the highest known reported result. Using the relaxed tolerances obtained from large spotsize lasers a very simple high performance laser package has also be produced. The combination of semiconductor device developments, silicon micromachining and novel packaging techniques has realised complicated optoelectronic modules which will give the technical performance and economic requirements needed for future optical telecommunication networks.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132392978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Statistical methods for stress screen development","authors":"M. R. Cooper","doi":"10.1109/ECTC.1996.550756","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550756","url":null,"abstract":"Stress screening during design, development, and production of electronic hardware is a quality improvement technique which can be employed to reduce defects in a product. However, due to the variety of electronic hardware types which may be screened and the number of stresses which may be applied for screening, there are no commercial standards which describe how to develop an effective stress screen. This paper describes a non-product-specific screen development technique which utilizes statistical analysis methods to achieve an effective and efficient stress screen. Statistical applications for various aspects of stress screen development are suggested, including Pareto analysis, Exploratory Data Analysis (EDA), Weibull analysis of time-to-failure data, comparison of means, analysis of variance (ANOVA), use of statistical process control charts (CUSUM, X-bar R), Duane plots of reliability growth, and use of the Poisson distribution for determining sample screen sizes. The techniques outlined involve test and analytical activities applied throughout product development; from first prototypes through to volume production. The use of statistical methods allows for development of an effective screen to remove defects and for an effective risk assessment of the effect of defects through numerical quantification of defect probabilities.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"198 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113967053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}