{"title":"Test vehicle for MCM-D interconnect process development","authors":"S. Westbrook","doi":"10.1109/MCMC.1993.302143","DOIUrl":"https://doi.org/10.1109/MCMC.1993.302143","url":null,"abstract":"A test vehicle that allows for the evaluation of DC interconnect parametrics of lines and vias is discussed. Defect assessment test structures are also included to electrically evaluate open and short defects and their apparent size. Interconnect parametrics include effective electrical linewidth, sheet resistance, and via resistance as a function of via size. Defect assessment structures are designed as multiple serpentine via string and line structures that aid in the unambiguous detection of defects. Such structures can also classify the apparent size of the defect. The data available from this vehicle show the degree of process control achieved and the potential yield of the interconnect for a product application.<<ETX>>","PeriodicalId":143140,"journal":{"name":"Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121053838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"FDTD modeling of noise in computer packages","authors":"Wendy S. Becker, R. Mittra","doi":"10.1109/MCMC.1993.302140","DOIUrl":"https://doi.org/10.1109/MCMC.1993.302140","url":null,"abstract":"The electromagnetic modeling of the components of a computer package that contribute to noise on the signal lines in computer packages is discussed. Equivalent circuits of coupled transmission lines, discontinuities in transmission lines, and a parallel-plate power plane configuration are obtained. These equivalent circuits allow one to use a circuit simulator to model the crosstalk, reflection, and simultaneous switching noises that are common in computer packages. The finite difference time domain (FDTD) algorithm is used to obtain the full-wave electromagnetic field solutions from which the equivalent circuits are determined.<<ETX>>","PeriodicalId":143140,"journal":{"name":"Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115877715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"iPROMIS: an interactive performance driven multilayer MCM router","authors":"M. Sriram, S.M. Kang","doi":"10.1109/MCMC.1993.302132","DOIUrl":"https://doi.org/10.1109/MCMC.1993.302132","url":null,"abstract":"Some of the physical design algorithms developed for iPROMIS, an interactive MCM physical design tool under development, are discussed. A performance-driven routing algorithm based on a new second-order delay model for lossy transmission lines and a multilayer assignment algorithm are described. A fast algorithm for computing the step response of interchip interconnections is also presented.<<ETX>>","PeriodicalId":143140,"journal":{"name":"Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129047599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Viking SuperSPARC AMCM development program","authors":"C. Eichelberger, H. Davidson","doi":"10.1109/MCMC.1993.302157","DOIUrl":"https://doi.org/10.1109/MCMC.1993.302157","url":null,"abstract":"A program to develop a Viking SuperSparc AMCM is discussed. The program is structured not only to provide a prototype module, but also to resolve key infrastructure issues associated with volume production of the module. The AMCM technology was chosen to fabricate the module. This technology is a chips first approach and offers important advantages in thermal management, power delivery, size and system interface. The program is divided into four phases. The first phase completes the Viking AMCM design and layout. The second phase fabricates and tests first articles. The third place demonstrates bare chip test and burn-in. The final phase produces preproduction qualification samples.<<ETX>>","PeriodicalId":143140,"journal":{"name":"Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128466532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Forman, C. A. Becker, M. Eskew, R. Huegel, D. Smith, R. Jordan
{"title":"End users access to prototype and production MCMs","authors":"G. Forman, C. A. Becker, M. Eskew, R. Huegel, D. Smith, R. Jordan","doi":"10.1109/MCMC.1993.302152","DOIUrl":"https://doi.org/10.1109/MCMC.1993.302152","url":null,"abstract":"The authors point out that the GE high density interconnect multichip module (HDI MCM) process has been broadly applied to many types of advanced system architectures, and recently the CAD technology has been transferred into the hands of a community of system designers. This HDI CAD process is based on a commercial, non-proprietary tool suite that has been successfully utilized at more than 10 remote sites. The dissemination of the GE HDI design methodology to various sites is detailed, and the CAD tools and techniques involved with the HDI interface to both the GE prototype and TI Merchant MCM Foundry are compared. Several HDI project case studies involving CAD tool usage and module production, from chip procurement and design transition to finished, tested modules, are described.<<ETX>>","PeriodicalId":143140,"journal":{"name":"Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132993337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}