发布求助
文献互助 智能选刊 最新文献

International Journal of Electronics Letters最新文献

筛选
英文 中文
Physical-layer security with frequency diverse array for DF multi-antenna relaying SWIPT system DF多天线中继SWIPT系统的分频阵列物理层安全
International Journal of Electronics Letters Pub Date : 2022-06-08 DOI: 10.1080/21681724.2022.2087911
Ji Jian, Bang Huang, Wen-qin Wang
{"title":"Physical-layer security with frequency diverse array for DF multi-antenna relaying SWIPT system","authors":"Ji Jian, Bang Huang, Wen-qin Wang","doi":"10.1080/21681724.2022.2087911","DOIUrl":"https://doi.org/10.1080/21681724.2022.2087911","url":null,"abstract":"ABSTRACT In this letter, we establish physical-layer security based on frequency diverse array (FDA) together with directional modulation (DM) for decode and forward (DF) relaying simultaneous wireless information and power transfer (SWIPT) system. The analytical expressions of the ergodic system secrecy capacity under the time switching (TS) protocol are derived. Moreover, the impacts of system parameters on secure performance are analysed. Numerical results reveal that the proposed method achieves better security performance than conventional PA solutions, especially in the range dimension.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"291 - 299"},"PeriodicalIF":0.0,"publicationDate":"2022-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46872050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
First order universal filters employing single DV-EXCCCII 采用单dv - exccii的一阶通用滤波器
International Journal of Electronics Letters Pub Date : 2022-06-07 DOI: 10.1080/21681724.2022.2087913
Priyanka Singh, R. Nagaria
{"title":"First order universal filters employing single DV-EXCCCII","authors":"Priyanka Singh, R. Nagaria","doi":"10.1080/21681724.2022.2087913","DOIUrl":"https://doi.org/10.1080/21681724.2022.2087913","url":null,"abstract":"ABSTRACT This paper reports two filter circuits based on Differential Voltage Extra-X Current Controlled Current Conveyor (DV-EXCCCII). The first proposed circuit is a voltage-mode first-order universal filter that employs one DV-EXCCCII, one resistor, and one grounded capacitor. This circuit can realise all standard first-order filters, that is, low-pass, high-pass and all-pass filter. The second proposed circuit is a first-order multimode universal filter that employs a single DV-EXCCCII. This circuit can realise filter in current-mode, voltage-mode and trans-admittance mode with a single capacitor. However, a trans-impedance mode universal filter is realised with an additional resistor. Furthermore, the filter is electronically tunable with the bias current of DV-EXCCCII. The proposed filter circuits are verified using the SPECTRE simulator of CADENCE VIRTUOSO tool in 0.18 µm UMC CMOS technology parameters.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"316 - 338"},"PeriodicalIF":0.0,"publicationDate":"2022-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47318153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Single-chip DC–DC buck converter design based on PWM with high-efficiency in light load 基于PWM的轻载高效率单片DC-DC降压变换器设计
International Journal of Electronics Letters Pub Date : 2022-05-11 DOI: 10.1080/21681724.2022.2068661
Chua-Chin Wang, O. L. J. A. Jose, Pang-Yen Lou, Chung-Jye Hsu, L. K. Tolentino, R. Sangalang
{"title":"Single-chip DC–DC buck converter design based on PWM with high-efficiency in light load","authors":"Chua-Chin Wang, O. L. J. A. Jose, Pang-Yen Lou, Chung-Jye Hsu, L. K. Tolentino, R. Sangalang","doi":"10.1080/21681724.2022.2068661","DOIUrl":"https://doi.org/10.1080/21681724.2022.2068661","url":null,"abstract":"ABSTRACT This research illustrates a DC–DC buck converter with a pulse width modulation (PWM) feedback control loop and capable of power supply voltage range from VDD to 2.5× VDD, which is equivalent to 5–14 V. It is a single chip with area of 1.379 × 0.813 mm2 using 0.5 µm HV CMOS process, where high voltage (HV) MOSFETs, a Dead-time detector, a PWM feedback loop, a control circuit and HV driving transistors are included. The main feature of our design is its capability of shutting off an optimal number of power MOSFETs during light load operation, resulting in a very high conversion efficiency. Most important of all, the optimal solution is analytically proved. The light load efficiency is raised from 31.71% by traditional methods to 67.94% by the proposed design.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"255 - 266"},"PeriodicalIF":0.0,"publicationDate":"2022-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45525810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Practical method for nullifying ripple effect from FIR-Hilbert transformer 消除FIR Hilbert变换器纹波效应的实用方法
International Journal of Electronics Letters Pub Date : 2022-05-02 DOI: 10.1080/21681724.2022.2062792
Kazuhiro Daikoku
{"title":"Practical method for nullifying ripple effect from FIR-Hilbert transformer","authors":"Kazuhiro Daikoku","doi":"10.1080/21681724.2022.2062792","DOIUrl":"https://doi.org/10.1080/21681724.2022.2062792","url":null,"abstract":"ABSTRACT When an FIR-Hilbert transformer with an even-numbered filter order of N is used in real-time signal processing, a delay line should be placed in parallel to compensate for the delay time of N/2 arising from the FIR-Hilbert transformer. In general, the FIR-Hilbert transformer possesses a ripple governed by a filter order, a transition bandwidth, among others. In contrast, the delay line does not possess any ripple. Then, an issue regarding the ripple is encountered during signal processing. In this letter, a practical method is proposed to nullify the ripple effect in signal processing. A simple solution is that the same ripple exists on the Hilbert transformer and delay line. Subsequently, two Weaver’s modulators for generating the USB signal are placed in parallel, and the real part of one of the two is used for a delay line and the imaginary part of the other of the two is used for a Hilbert transformer. When the same FIR-LPF is introduced into each of the two, the ripple effect can be nullified.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"157 - 164"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47802424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of approximate reverse carry select adder using RCPA 基于RCPA的近似反向进位选择加法器设计
International Journal of Electronics Letters Pub Date : 2022-04-29 DOI: 10.1080/21681724.2022.2062791
Rajasekhar Turaka, Koteswar Rao Bonagiri, Talla Srinivasa Rao, G. Kumar, Sudharsan Jayabalan, V. Sreenivasulu, Asisa Kumar Panigrahy, M. Prakash
{"title":"Design of approximate reverse carry select adder using RCPA","authors":"Rajasekhar Turaka, Koteswar Rao Bonagiri, Talla Srinivasa Rao, G. Kumar, Sudharsan Jayabalan, V. Sreenivasulu, Asisa Kumar Panigrahy, M. Prakash","doi":"10.1080/21681724.2022.2062791","DOIUrl":"https://doi.org/10.1080/21681724.2022.2062791","url":null,"abstract":"ABSTRACT An approximate carry select adder (CSLA) with reverse carry propagation (RCSLA) is showed in this work. This RCSLA was designed with reverse carry propagate full adder (RCPFA). In RCPFA structure, the carry signal propagates in the reverse direction that is from MSB part to LSB part, then the carry input has greater importance compared to the output carry. Three types of implementations were designed in RCPFA based on the design parameters. This method was applied to RCA & CSLA to design other types of approximate adders. These designs and simulations were done in CADENCE Software tool with 45 nm COMS technology. The design parameters of the three CSLA implementations with RCPFA are compared with the existing CSLA adders.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"146 - 156"},"PeriodicalIF":0.0,"publicationDate":"2022-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45036699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
X-band Miniaturized frequency reconfigurable travelling wave antenna x波段小型化频率可重构行波天线
International Journal of Electronics Letters Pub Date : 2022-04-25 DOI: 10.1080/21681724.2022.2068194
Narjala Sri Pravallika, V. Anitha, K. Rama Naidu
{"title":"X-band Miniaturized frequency reconfigurable travelling wave antenna","authors":"Narjala Sri Pravallika, V. Anitha, K. Rama Naidu","doi":"10.1080/21681724.2022.2068194","DOIUrl":"https://doi.org/10.1080/21681724.2022.2068194","url":null,"abstract":"ABSTRACT The paper presents a novel miniaturized (1.2 λ0 × 0.5 λ0 × 0.026 λ0 ) frequency reconfigurable travelling wave antenna (TWA) operating at 8–12 GHz band. The antenna uses PIN diodes arranged in a novel configuration to produce frequency reconfigurability and operates at single frequency bands of 8.5, 9, 9.35, 9.9, 10.45 and 11 GHz with an average bandwidth of 1 GHz based on different switch configurations. The proposed antenna demonstrates an efficiency>80% for the operating frequency in different stations while maintaining a stable average gain of 8.5 dBi. The antenna’s compact nature and high gain make it suitable for several applications within modern satellite communication devices and radar systems. The proposed antenna is designed and tested for its conformality using CST Microwave-Studio. The proposed design is further verified with a fabricated prototype measured in an anechoic chamber, agreeing well with the simulated results.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"221 - 231"},"PeriodicalIF":0.0,"publicationDate":"2022-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47745557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Femto power-delay(FPD)super threshold level shifter for network on chip (NoC) 用于片上网络（NoC）的毫微微功率延迟（FPD）超阈值电平移位器
International Journal of Electronics Letters Pub Date : 2022-04-22 DOI: 10.1080/21681724.2022.2068660
Srinivasulu Gundala, M. Mahaboob Basha, R. Busi
{"title":"Femto power-delay(FPD)super threshold level shifter for network on chip (NoC)","authors":"Srinivasulu Gundala, M. Mahaboob Basha, R. Busi","doi":"10.1080/21681724.2022.2068660","DOIUrl":"https://doi.org/10.1080/21681724.2022.2068660","url":null,"abstract":"ABSTRACT This paper presents a novel architecture of femto power-delay super threshold voltage level shifter (LS) for network on-chip voltage control, developed using feedback topology for error aware interconnections data transmission. The proposed LS utilises eight MOS transistors with low aspect ratios for level up or level down. The developed LS can shift as low as 0.12–1.25 V with a tremendous reduction in delay and power consumption. Implemented in 65 nm CMOS technology, the post-layout simulation substantiates the achievement of voltage translation. The proposed LS incurs energy per cycle of 44 fJ during up shift; the average of level up and level down static power consumption is 3.61 nW, while VDDL is 0.3 V and VDDH is 1.2 V at a frequency of 1 MHz. The layout area of the proposed LS is 3.21 µm × 2.13 µm.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"241 - 253"},"PeriodicalIF":0.0,"publicationDate":"2022-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49008173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Sense amplifier for ReRAM-based crossbar memory systems 基于reram的交叉棒存储系统的感测放大器
International Journal of Electronics Letters Pub Date : 2022-04-19 DOI: 10.1080/21681724.2022.2067903
Hock Leong Chee, Yufeng Kok, T. N. Kumar, Haider A. F. Almurib
{"title":"Sense amplifier for ReRAM-based crossbar memory systems","authors":"Hock Leong Chee, Yufeng Kok, T. N. Kumar, Haider A. F. Almurib","doi":"10.1080/21681724.2022.2067903","DOIUrl":"https://doi.org/10.1080/21681724.2022.2067903","url":null,"abstract":"ABSTRACT A voltage-mode sense amplifier circuit designed for resistive random-access memory (ReRAM)-based memory arrays is proposed. The sense amplifier is designed comprising of an inverting buffer so that it can operate at a very low voltage (150 mV), which is the typical READ output voltages of a ReRAM cell while the proposed differential comparator design utilises a reduced number of transistors (20%) compared with conventional design to determine the logic states of the ReRAM cell. A simulation with a 2 × 2 memory crossbar is performed and compared with existing voltage-mode and current-mode sense amplifiers and the proposed circuit shows better READ time (32% and 85%) and energy performance (54% and 59%) than existing methods.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"180 - 192"},"PeriodicalIF":0.0,"publicationDate":"2022-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46879472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
FPGA Implementation of Polyphase Digital Down Converter for WiMAX Systems WiMAX系统多相数字下变频的FPGA实现
International Journal of Electronics Letters Pub Date : 2022-04-19 DOI: 10.1080/21681724.2022.2068659
Debarshi Datta, H. Dutta
{"title":"FPGA Implementation of Polyphase Digital Down Converter for WiMAX Systems","authors":"Debarshi Datta, H. Dutta","doi":"10.1080/21681724.2022.2068659","DOIUrl":"https://doi.org/10.1080/21681724.2022.2068659","url":null,"abstract":"ABSTRACT This paper briefs the implementation of a reconfigurable digital down converter (DDC) on a field-programmablegate array (FPGA) development board to be used in worldwide interoperability for microwave access (WiMAX) applications. The proposed polyphase design includes a parallel number of coordinate rotation digital computer (CORDIC) processors and low-passfinite impulse response (FIR) filters. Furthermore, the single rate FIR filter works with complex data input using canonical implementation. This strategy reduces multiplications and computational complexity. Additionally, the sample rate factor can be dynamically reconfigured to support multistandard DDC architectures. The mathematical expressions of the proposed design are briefly described. Comparison results indicate that the proposed design saves the hardware resources to achieve a cost-effectivesolution for software-definedradio standards. The simulation and experimental results are used to verify the correctness and feasibility of the polyphase DDC structure.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"232 - 240"},"PeriodicalIF":0.0,"publicationDate":"2022-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48756610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Power grid stability identification using high discriminative factors 基于高判别因子的电网稳定性识别
International Journal of Electronics Letters Pub Date : 2022-04-19 DOI: 10.1080/21681724.2022.2068192
Hosein Eskandari, M. Imani, M. Parsa Moghaddam
{"title":"Power grid stability identification using high discriminative factors","authors":"Hosein Eskandari, M. Imani, M. Parsa Moghaddam","doi":"10.1080/21681724.2022.2068192","DOIUrl":"https://doi.org/10.1080/21681724.2022.2068192","url":null,"abstract":"ABSTRACT The aim of this work is stability identification considering influence of different factors such as reaction time, nominal power and price elasticity of consumers and producers in stability situation of the power grid. The binary coding-based feature weighting (BCFW) method is introduced. The proposed method assigns greater weights to the factors with higher ability in separation between stable and unstable states in the classification process. To this end, the binary vectors of the first statistics of the data samples are generated. According to the defined binary vector for each factor (feature), that factor belongs to one of four possible states. While two possible states are appropriate for separation of stable from unstable situations, two other ones are inappropriate for this purpose. Feature weighting is done according to the defined states. The proposed method shows superior performance compared to support vector machine (SVM), multinomial logistic regression (MLR), convolutional neural network (CNN), maximum likelihood (ML) and nearest neighbour (NN), especially using limited training samples. With using just 1% training samples, the proposed BCFW method identifies the stability situation with 80.01% overall accuracy, while SVM, MLR, CNN, ML and NN achieve 79.41%, 79.05%, 71.91%, 71.24% and 64.04% overall accuracy, respectively.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"193 - 202"},"PeriodicalIF":0.0,"publicationDate":"2022-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49566033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信