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Performance of multi-antenna relay based cooperative spectrum sensing in cognitive radio network 认知无线电网络中基于多天线中继的协同频谱感知性能研究
International Journal of Electronics Letters Pub Date : 2021-10-06 DOI: 10.1080/21681724.2021.1969434
Rupali Agarwal, Neelam Srivastava, H. Katiyar
{"title":"Performance of multi-antenna relay based cooperative spectrum sensing in cognitive radio network","authors":"Rupali Agarwal, Neelam Srivastava, H. Katiyar","doi":"10.1080/21681724.2021.1969434","DOIUrl":"https://doi.org/10.1080/21681724.2021.1969434","url":null,"abstract":"ABSTRACT In this paper, we analyse the performance of infrastructure-based fixed relay with multi-antenna in cognitive radio. We derive the mathematical expression for detection probability of single cooperative relay system over Rayleigh fading channel. Relay and fusion centre may perform either selection combining or maximal ratio combining of the signals. Effect of number of relay antennas for all four combinations of combining schemes has been analysed and as expected, increase in relay diversity improves the sensing performance. This is because, on installing more number of receiving antennas on the relay, it’s participation increases, so the detection performance also improves. In the non-cooperative system also, the performance improves on increasing the diversity order but on the other hand, this increment imposes burden on the fusion centre. Whereas in multi-antenna cooperative relay system, the burden of relay gets transferred on relay node and the fusion centre takes advantage of increased diversity order of relay. For cooperative spectrum sensing, we have used soft decision combining scheme in which secondary users send their test statistics calculated from their local observations.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"10 1","pages":"414 - 427"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43650878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low Power Voltage Spike Detection Circuit for Cap-less LDO 一种无帽LDO低功率电压尖峰检测电路
International Journal of Electronics Letters Pub Date : 2021-09-02 DOI: 10.1080/21681724.2021.1966657
P. Manikandan, B. Bindu
{"title":"A Low Power Voltage Spike Detection Circuit for Cap-less LDO","authors":"P. Manikandan, B. Bindu","doi":"10.1080/21681724.2021.1966657","DOIUrl":"https://doi.org/10.1080/21681724.2021.1966657","url":null,"abstract":"ABSTRACT A low-power voltage spike detection (VSD) circuit for a cap-less low-dropout regulator (LDO) is presented in this paper. The LDO is based on the cascoded flipped voltage follower (CAFVF) topology, and the transients in the output voltage are controlled by the spike detection circuits and these circuits get activated only during the transient period. The overshoot voltage spike detection (OVSD) circuit senses the output voltage via intermediate voltage and reduces the current through the power MOSFET by charging the gate capacitance and restores the output voltage whenever the output voltage rises. The undershoot voltage spike detection (UVSD) circuit directly detects the output voltage and increases the current through the power MOSFET by discharging the gate capacitance and restores back the output voltage whenever the output voltage drops. The VSD circuit consumes only a bias current of in the steady state. This LDO is implemented in CMOS technology and achieved a good load transient response with settling time with the maximum voltage spike of over the load current range of to .","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"10 1","pages":"377 - 390"},"PeriodicalIF":0.0,"publicationDate":"2021-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46753341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-cost ELC-UWB fan-shaped antenna using parasitic SRR triplet for ISM band and PCS applications 低成本ELC-UWB扇形天线，使用寄生SRR三元组，用于ISM频带和PCS应用
International Journal of Electronics Letters Pub Date : 2021-09-02 DOI: 10.1080/21681724.2021.1966655
Atul Varshney, Nishigandha Cholake, Vipul K. Sharma
{"title":"Low-cost ELC-UWB fan-shaped antenna using parasitic SRR triplet for ISM band and PCS applications","authors":"Atul Varshney, Nishigandha Cholake, Vipul K. Sharma","doi":"10.1080/21681724.2021.1966655","DOIUrl":"https://doi.org/10.1080/21681724.2021.1966655","url":null,"abstract":"ABSTRACT This article presents a low-cost, fan-shaped, tri-arm, circular microstrip antenna that is practically loaded with the three split-ring resonators (SRR) and also uses defected ground structure (DGS) to obtain ultra-wideband (UWB) performance. To compensate for the decreased value of gain because of the DGS structure, the antenna is further loaded parasitically with three split-ring resonators (SRR). The introduced metamaterial SRR triplet results in improved impedance matching and 7 dB improvement in reflection coefficient (S11) at the designed frequency. This also leads to improvement in the gain of antenna and a gain of 7.16 dBi has been obtained. The paper reports 10 dB bandwidth from 1.81 GHz to 3.0 GHz which covers applications like Wi-MAX, Wi-Fi, GSM (1.9 GHz), public safety band, Bluetooth, ISM band (2.4–2.5 GHz), 3 G (2.1 GHz), 4 G LTE(2.1–2.5 GHz), WCDMA (1.9, 2.1 GHz) and other PCS applications. The measured values of S11 is lower than −10 dB for the fractional bandwidth more than 48.98% and hence ultra-wideband performance has been achieved. The antenna is novel in the sense it contains three fractal rectangular arms in the basic circular patch. The addition of arms in patch increases the overall electrical length, which results in improvement in overall bandwidth.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"10 1","pages":"391 - 402"},"PeriodicalIF":0.0,"publicationDate":"2021-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44726126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A wideband millimetre-wave antenna array for 5G and next generation thin mobile terminals 一种用于5G及下一代轻薄移动终端的宽带毫米波天线阵列
International Journal of Electronics Letters Pub Date : 2021-08-27 DOI: 10.1080/21681724.2021.1966654
Yifan Yu, Yongle Wu, Weimin Wang, Yuhao Yang
{"title":"A wideband millimetre-wave antenna array for 5G and next generation thin mobile terminals","authors":"Yifan Yu, Yongle Wu, Weimin Wang, Yuhao Yang","doi":"10.1080/21681724.2021.1966654","DOIUrl":"https://doi.org/10.1080/21681724.2021.1966654","url":null,"abstract":"ABSTRACT A millimetre-wave antenna array with a wide bandwidth and a high return loss for 5G and next generation thin mobile terminals is presented in this paper. The proposed antenna array is designed on the basis of the E-shaped patch antenna elements and an H-shaped feed network, and it uses the multilayer patch structure to achieve broad bandwidth. According to the simulated and measured results, the 15-dB bandwidth of the antenna array can cover 30.85–34.36 GHz. The proposed design is made of low-cost Rogers laminates with a simple structure so that it can be used in thin mobile terminals.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"10 1","pages":"367 - 376"},"PeriodicalIF":0.0,"publicationDate":"2021-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45355054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power optimisation of single phase clocked feedback D flip-flop for CDMA CDMA中单相时钟反馈D触发器的功率优化
International Journal of Electronics Letters Pub Date : 2021-08-26 DOI: 10.1080/21681724.2021.1966653
Y. Gajare, A. Khaparde
{"title":"Power optimisation of single phase clocked feedback D flip-flop for CDMA","authors":"Y. Gajare, A. Khaparde","doi":"10.1080/21681724.2021.1966653","DOIUrl":"https://doi.org/10.1080/21681724.2021.1966653","url":null,"abstract":"ABSTRACT A low power flip-flop is demanding delay element in digital sigma delta modulator of DAC system. This paper highlights power optimisation of single-phase clocked feedback D flip-flop using various optimisation techniques like clock gating, MTCMOS etc. In this scenario, clock gating using GDI and single-phase clocked inverter is invented to avoid unwanted no data transitions of flip-flop, also proposed type is compared with existing techniques. In addition to this, full swing GDI (gate-Diffusion Input) cell itself is modified by single phase clocked inverter to minimise threshold voltage drop and unwanted spikes at the output. There is trade off in area, speed and power. This work is based on power optimisation with favourable speed and area. Flip-flop is verified for clock frequency of 50 MHz as well as CDMA (Code Division Multiple Access) frequency of 1.6 MHz. Analysis is carried out in SPECTRE simulator of CADENCE environment with 180 nm technology supplied by AMS. Not only power but delay is also measured to check the performance of flip-flop. Proposed circuit gives 92.8% power and power delay product improvement.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"10 1","pages":"354 - 366"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47773800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Enhanced asymmetric DDSCR with high robustness for high-voltage ESD protection 高稳健性的增强型非对称DDSCR用于高压ESD保护
International Journal of Electronics Letters Pub Date : 2021-08-25 DOI: 10.1080/21681724.2021.1969435
Yang Wang, Jieyu Li, Weipeng Wei, Pei Cao, Wenmiao Cao
{"title":"Enhanced asymmetric DDSCR with high robustness for high-voltage ESD protection","authors":"Yang Wang, Jieyu Li, Weipeng Wei, Pei Cao, Wenmiao Cao","doi":"10.1080/21681724.2021.1969435","DOIUrl":"https://doi.org/10.1080/21681724.2021.1969435","url":null,"abstract":"ABSTRACT This paper proposes an enhanced asymmetric dual directional silicon controlled rectifier (EADDSCR) for the applications of bidirectional electrostatic discharge (ESD) protection. The ADDSCR and EADDSCR were prepared in a 0.18 µm Bipolar CMOS DMOS (BCD) process and measured with the transmission line pulsing tester. By adding N+ injection regions in the cathode and anode, a new vertical SCR path is formed in EADDSCR, so that the failure current of EADDSCR can reach twice as much as that of ADDSCR with only a small increase in the area of EADDSCR. Moreover, the FoM of EADDSCR can be increased to more than 81.19 µA/µm. Finally, the improved device possesses a smaller on resistance and is more suitable for high-voltage circuit applications.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"10 1","pages":"428 - 435"},"PeriodicalIF":0.0,"publicationDate":"2021-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45828063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Realisation of overflow oscillation-free fixed-point digital filters with 2’s complement arithmetic 用2的补码算法实现无溢出振荡定点数字滤波器
International Journal of Electronics Letters Pub Date : 2021-08-14 DOI: 10.1080/21681724.2021.1969436
Shimpi Singh, H. Kar
{"title":"Realisation of overflow oscillation-free fixed-point digital filters with 2’s complement arithmetic","authors":"Shimpi Singh, H. Kar","doi":"10.1080/21681724.2021.1969436","DOIUrl":"https://doi.org/10.1080/21681724.2021.1969436","url":null,"abstract":"ABSTRACT In this paper, we focus on the problem of overflow oscillation elimination in 2’s complement state variable realisation of fixed-point digital filters. A new global asymptotic stability (GAS) criterion for the zero-input fixed-point state-space digital filters employing 2’s complement overflow arithmetic is proposed. The proposed criterion captures the structural properties of 2’s complement overflow nonlinearities in a greater detail as compared to several existing criteria. A comparative evaluation of the proposed criterion with various previously reported criteria is made. The obtained criterion turns out to be less stringent than several existing results. An example along with simulation results to substantiate the utility of the criterion is also provided.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"10 1","pages":"436 - 446"},"PeriodicalIF":0.0,"publicationDate":"2021-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48585059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Cap layer effect in DC and RF characteristics of InP based n-p-n metamorphic δ-doped heterojunction bipolar transistor InP基n-p-n变质δ掺杂异质结双极晶体管直流和射频特性中的帽层效应
International Journal of Electronics Letters Pub Date : 2021-07-07 DOI: 10.1080/21681724.2021.1941280
M. Jena, A. Diwarkar, A. Panda, G. Dash
{"title":"Cap layer effect in DC and RF characteristics of InP based n-p-n metamorphic δ-doped heterojunction bipolar transistor","authors":"M. Jena, A. Diwarkar, A. Panda, G. Dash","doi":"10.1080/21681724.2021.1941280","DOIUrl":"https://doi.org/10.1080/21681724.2021.1941280","url":null,"abstract":"ABSTRACT The effect of InGaAsP and InGaAs cap layers in InP n-p-n heterojunction bipolar transistor (HBT) is presented. The common figures of merit (FOM) in each case are compared to assess their potentials for operation at high frequency. The Gummel-Poon plot of experimental reported result has been used to validate the data obtained from simulation using ATLAS module of Silvaco software tool. After models validation in TCAD tool, the DC and RF characteristics of the HBTs with different cap layers are examined and then a comparative analysis is carried out based on the characteristics such as I–V behaviour, frequency response, minimum noise figure and maximum cut-off frequency. With the change in InGaAs cap to InGaAsP cap, the DC current gain increases from 255 to 300, VCE,offset is reduced from 131 to 76 mV, Early Voltage (VA) increases from −42 to −190 V, cut-off frequency ft is increased from 24.34 MHz to 8.04 GHz, and the maximum oscillation of frequency(fmax) is improves from 13.79 to 37.11 GHz","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"10 1","pages":"308 - 320"},"PeriodicalIF":0.0,"publicationDate":"2021-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1080/21681724.2021.1941280","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45960026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A PSO based optimal repeater insertion technique for carbon nanotube interconnects 一种基于粒子群优化的碳纳米管互连中继器插入技术
International Journal of Electronics Letters Pub Date : 2021-06-24 DOI: 10.1080/21681724.2021.1941283
P. Uma Sathyakam, Shubham Raj, A. Karthikeyan, P. S. Mallick
{"title":"A PSO based optimal repeater insertion technique for carbon nanotube interconnects","authors":"P. Uma Sathyakam, Shubham Raj, A. Karthikeyan, P. S. Mallick","doi":"10.1080/21681724.2021.1941283","DOIUrl":"https://doi.org/10.1080/21681724.2021.1941283","url":null,"abstract":"ABSTRACT Optimal repeater insertion is important in VLSI(very large scale integration) interconnects to reduce propagation delay and power dissipation. We propose a particle swarm optimisation (PSO)-based optimal repeater number for different lengths of carbon nanotube (CNT) interconnects at 20 nm and 14 nm technology nodes. First, numerical equations for optimal repeaters are modelled. Secondly, a PSO-based algorithm is developed and various input parameters are used to train the PSO. Optimal number of repeaters and the propagation delay for CNT interconnects for lengths ranging from 500 to 2000 µm are found out. Results are compared for both numerical and PSO methods, and it is found that they are within 2% deviation. Although earlier work shows similar findings, we have used CNTFET(carbon nanotube field effect transistor)-based inverters as repeaters in CNT interconnects for the first time. We have carried out the analysis for two values of repeater size, i.e. h = 50 and 75.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"10 1","pages":"344 - 353"},"PeriodicalIF":0.0,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1080/21681724.2021.1941283","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45729656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 17.5dB wide-dynamic range high-efficiency RF-to-DC power converter for wireless energy harvesting 用于无线能量收集的17.5dB宽动态范围高效rf - dc功率转换器
International Journal of Electronics Letters Pub Date : 2021-06-23 DOI: 10.1080/21681724.2021.1941281
Abdulaziz Alhoshany
{"title":"A 17.5dB wide-dynamic range high-efficiency RF-to-DC power converter for wireless energy harvesting","authors":"Abdulaziz Alhoshany","doi":"10.1080/21681724.2021.1941281","DOIUrl":"https://doi.org/10.1080/21681724.2021.1941281","url":null,"abstract":"ABSTRACT A novel reconfigurable RF-to-DC power converter is proposed for wireless energy harvesting. The proposed RF rectifier employs low-threshold transistors with cross-coupled configuration to enhance the flow of the forward current to the load at low input RF power and adaptive stacking diodes to reduce the leakage current by lowering the driving voltage of the rectifying PMOS transistors at high input RF power. The proposed rectifier utilises the body biasing technique to modulate the threshold voltage and minimises the leakage current of the feedback diodes. The proposed novel techniques improve efficiency and extend the dynamic range. The prototype is implemented in a 65 nm CMOS technology and occupies an active area of 0.0148 mm2. The proposed rectifier achieves a peak power conversion efficiency (PCE) of 76% with a load of a 100-KΩ load at the industrial, scientific, and medical band 433 MHz, and the achieved sensitivity of the rectifier is −18.5 dBm for 1 V DC output voltage. The proposed rectifier offers PCE at −35 dBm of 45.6%, which is the best low-power performance. Compared to the state-of-the-art rectifiers, the proposed design achieves an excellent wide-dynamic range of 17.5 dB, which is ten times better than the conventional cross-coupled rectifier.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"10 1","pages":"321 - 332"},"PeriodicalIF":0.0,"publicationDate":"2021-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1080/21681724.2021.1941281","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43023165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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