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Enhancement of output power level of RF energy harvesting circuit using Wilkinson power combiner 使用Wilkinson功率组合器提高射频能量采集电路的输出功率电平
International Journal of Electronics Letters Pub Date : 2022-01-03 DOI: 10.1080/21681724.2021.2025436
Joydeep Banerjee
{"title":"Enhancement of output power level of RF energy harvesting circuit using Wilkinson power combiner","authors":"Joydeep Banerjee","doi":"10.1080/21681724.2021.2025436","DOIUrl":"https://doi.org/10.1080/21681724.2021.2025436","url":null,"abstract":"ABSTRACT Different interesting research has been going on in the area of RF energy harvesting during the last decade. This paper presents the comparisons of different Schottky diode-based RF energy harvester circuits and cross-coupled MOS-based RF energy harvester circuits. An improvement at output power level is achieved. In this proposed work, the author has proposed a simple two-way Wilkinson power combiner to connect with these RF energy harvesting circuits for achieving a higher power level. The experimental output voltage of a three-stage diode-based Villard RF energy harvester circuit has been carried out. A Schottky diode-based Villard RF energy harvester circuit is tested at 600 MHz, and output voltage has been carried out. The circuit is also connected at 2.4 GHz Wi-Fi. A Monte Carlo simulation was also carried out to analyse the output parameters obtained from this proposed MOS-based circuits.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"1 - 16"},"PeriodicalIF":0.0,"publicationDate":"2022-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45077866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An efficient QCA-based full adder design with power dissipation analysis 一种基于QCA的高效全加器设计及功耗分析
International Journal of Electronics Letters Pub Date : 2022-01-03 DOI: 10.1080/21681724.2021.2025440
Ismail Gassoumi, L. Touil, A. Mtibaa
{"title":"An efficient QCA-based full adder design with power dissipation analysis","authors":"Ismail Gassoumi, L. Touil, A. Mtibaa","doi":"10.1080/21681724.2021.2025440","DOIUrl":"https://doi.org/10.1080/21681724.2021.2025440","url":null,"abstract":"ABSTRACT Quantum Dot-Cellular automata (QCA) is a developing technology that is considered as the best viable alternate solution for CMOS technology which has short-channel effects. QCA is a transistor-free technology, and the information is distributed formulated on the charge of the electron and by Columbic repulsion theory. In this paper, an optimal adder circuit is proposed using QCA technology which consist only 14 cells. The proposed adder circuit is further utilised for designing of 4-bit adder design efficiently. Simulations results, are obtained precisely using QCADesigner software version 2.0.3., confirm that the proposed circuits work well. Moreover, the energy dissipations of the proposed adder circuit design is estimated using QCAPro tool. The performance of the proposed design was compared with the existing ones which shows better performance in terms of cell count, area, and latency. Suggested 1-bit and 4-bit QCA adders exhibit a delay of 0.5 and 1.25 clock cycle, occupy an active area of 0.01 and 0.1 and μm2, and use 14 and 84 QCA cells, respectively.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"55 - 67"},"PeriodicalIF":0.0,"publicationDate":"2022-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47462194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Voltage-tunable immittance functions: Linear voltage-controlled quadrature oscillator implementation 电压可调阻抗函数:线性压控正交振荡器的实现
International Journal of Electronics Letters Pub Date : 2022-01-03 DOI: 10.1080/21681724.2021.2025441
K. Mathur, R. Nandi
{"title":"Voltage-tunable immittance functions: Linear voltage-controlled quadrature oscillator implementation","authors":"K. Mathur, R. Nandi","doi":"10.1080/21681724.2021.2025441","DOIUrl":"https://doi.org/10.1080/21681724.2021.2025441","url":null,"abstract":"ABSTRACT A new scheme on the realisation of voltage-tunable immittance function (VTIF) is proposed. Here two types of grounded, high-quality (Q) resonant filters and voltage-controlled quadrature oscillators (VCQO) with a linear tuning law are presented. Analysis indicates that the filter/QO parameters are impervious to the ABB parasitic components. Experimental results exhibit a VCQO-linear tuning range of fo ~14 MHz with a satisfactory phase-noise margin of immittances, viz., inductance (L) and frequency-dependent negative resistance (D) are derived using the Current Feedback Amplifier (CFA) combined with analog voltage-multiplier elements as the active building block (ABB). Subsequently, implementation of LC-bandpass and rD-band-reject selective filters, along with QO designs, is presented with low THD and phase noise of (─)104 dBc/Hz at 30 kHz offset. Experimental results of the proposed circuits had been satisfactorily verified using standard commercially available IC modules.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"68 - 79"},"PeriodicalIF":0.0,"publicationDate":"2022-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42171397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Nonlinear control of the boost converter subject to unknown constant power load and parasitics 未知恒功率负载和寄生作用下升压变换器的非线性控制
International Journal of Electronics Letters Pub Date : 2022-01-03 DOI: 10.1080/21681724.2021.2025438
Said Oucheriah
{"title":"Nonlinear control of the boost converter subject to unknown constant power load and parasitics","authors":"Said Oucheriah","doi":"10.1080/21681724.2021.2025438","DOIUrl":"https://doi.org/10.1080/21681724.2021.2025438","url":null,"abstract":"ABSTRACT A robust adaptive controller is developed to regulate the output voltage of the boost converter feeding an unknown constant power load (CPL) and subject to unknown parasitic parameters. The boost converter is a non-minimum phase system that is very prone to the destabilising effects of the negative incremental resistance of the CPL and presents a major challenge in the design of stabilising controllers. An adaptive controller is developed to tightly regulate the output voltage of the converter despite large load variations, parasitic elements in the converter parameters and instability effects induced by the CPL. A systematic procedure is developed to select the adaptive controller gains to achieve a satisfactory output response. Using simulation, the effectiveness of the proposed controller is validated and compared to a recent robust nonlinear controller.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"30 - 40"},"PeriodicalIF":0.0,"publicationDate":"2022-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"60455522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new high frequency MOS-C TOETQO employing DXCCTA 采用DXCCTA的新型高频MOS-C TOETQO
International Journal of Electronics Letters Pub Date : 2022-01-02 DOI: 10.1080/21681724.2021.2025435
Rubila Laishram, Manoj Joshi, A. Ranjan
{"title":"A new high frequency MOS-C TOETQO employing DXCCTA","authors":"Rubila Laishram, Manoj Joshi, A. Ranjan","doi":"10.1080/21681724.2021.2025435","DOIUrl":"https://doi.org/10.1080/21681724.2021.2025435","url":null,"abstract":"ABSTRACT This research paper reports a high frequency Third Order Electronically Tunable Quadrature Oscillator (TOETQO) using an active element termed as Dual-X Current Conveyor Transconductor Amplifier (DXCCTA) in which active element MOS and passive Capacitor (C) contribute the implementation performance of the proposed design as MOS-C TOETQO. Due to the presence of DXCCTA with active grounded capacitor and MOS-based resistor, the proposed quadrature oscillator facilitates a suitable design for integrated circuits (ICs). The proposed TOETQO circuit produces current as well as voltage outputs simultaneously. Moreover, the non-ideal analysis of the proposed oscillator circuit is also included. The proposed design shows a good agreement for the oscillation criteria due to the acceptable limit of %THD and gives the variation in frequency of oscillation (up to MHz) values with respect to bias current. Moreover, by keeping the bias current constant, frequency of oscillation can also be electronically tuned independently by varying the values of resistor. Finally, Cadence simulation results are depicted to verify the theoretical analyses and practical feasibility of proposed TOETQO design is also well verified with experimental set up by using IC AD844 and CA3080. A fair comparison of the proposed quadrature oscillator with existing literatures is also tabulated.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"10 1","pages":"505 - 520"},"PeriodicalIF":0.0,"publicationDate":"2022-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42324518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A universal current-mode current conveyor filter based on GFET inverter 一种基于GFET逆变器的通用电流型电流输送滤波器
International Journal of Electronics Letters Pub Date : 2021-11-26 DOI: 10.1080/21681724.2021.2001848
A. Safari
{"title":"A universal current-mode current conveyor filter based on GFET inverter","authors":"A. Safari","doi":"10.1080/21681724.2021.2001848","DOIUrl":"https://doi.org/10.1080/21681724.2021.2001848","url":null,"abstract":"ABSTRACT CMOS technology faces significant challenges at the nanoscale. Graphene-based electronics has emerged as a feasible promising to continue obeying Moore’s law. In this paper, a positive-type second-generation current conveyor (CCII+) builds with Graphene FET (GFET) inverters is proposed. A universal current-mode active filter is presented which can realise all standard filter functions employing CCII+ as an active element. The performance of the GFET filter was simulated and analysed with 0.18um GFET technology using ADS tools. The simulation results demonstrate that the proposed GFET filter consumes 1.2 mW at 10 MHz with ±0.5 V supply voltage. Furthermore, the centre frequency of the proposed filter can be tuned electronically. As an application, a quadrature oscillator example is given. The performance of first active filter based on GFET Current conveyor is compared with CMOS technology.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"10 1","pages":"475 - 488"},"PeriodicalIF":0.0,"publicationDate":"2021-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"60455692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development of high power 20 dB directional coupler for Ion Cyclotron Resonance frequency system of Tokamak 托卡马克离子回旋共振频率系统大功率20dB定向耦合器的研制
International Journal of Electronics Letters Pub Date : 2021-11-17 DOI: 10.1080/21681724.2021.2001849
Abhinav Jain, R. Yadav
{"title":"Development of high power 20 dB directional coupler for Ion Cyclotron Resonance frequency system of Tokamak","authors":"Abhinav Jain, R. Yadav","doi":"10.1080/21681724.2021.2001849","DOIUrl":"https://doi.org/10.1080/21681724.2021.2001849","url":null,"abstract":"ABSTRACT This article presents the design and fabrication of 20 ± 0.3 dB directional coupler having 2 kW power handling capability in the frequency range of 140–200 MHz. The developed coupler has an important application in the prototype of the Ion Cyclotron Resonance Frequency (ICRF) system of Tokamak. The directional coupler used to couple the forward and reflected power for measurement and provide the feedback to the existing matching network responsible for protecting the high-power RF source. The developed coupler is compact in size, robust, and capable of handling 2 kW, continuous wave (CW) RF power. This paper also analyses the dielectric breakdown strength using electric field distribution inside the coupler, and the average power handling capability is determined using numerical analysis. The test results using Vector Network Analyser (VNA) are obtained as, the coupling flatness of 20 ± 0.3 in 140–200 MHz frequency range, return loss and isolation are −30 dB and −35 dB, respectively. The work presented in this paper is helpful for the development of high-power coupler in radio frequency (RF) range and may be applied in various applications such as RF Plasma, Radar, navigation, satellite, and research, etc.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"10 1","pages":"489 - 504"},"PeriodicalIF":0.0,"publicationDate":"2021-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44738598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
3D prism shaped circularly polarised MIMO diversity antenna with 360o angular coverage 具有360度角覆盖的三维棱柱形圆极化MIMO分集天线
International Journal of Electronics Letters Pub Date : 2021-11-09 DOI: 10.1080/21681724.2021.2001847
Prashant Chaudhary, Ashwani Kumar, Kamlesh Patel, R. Arya, Maifuz Ali, A. Verma
{"title":"3D prism shaped circularly polarised MIMO diversity antenna with 360o angular coverage","authors":"Prashant Chaudhary, Ashwani Kumar, Kamlesh Patel, R. Arya, Maifuz Ali, A. Verma","doi":"10.1080/21681724.2021.2001847","DOIUrl":"https://doi.org/10.1080/21681724.2021.2001847","url":null,"abstract":"ABSTRACT This paper presents the 3D prism-shaped circularly polarised MIMO Diversity Antenna with 360° angular coverage. The proposed antenna has six elements, and it covers the X-band with impedance matching from 8.0 to 11.8 GHz (38.4%), 3 dB axial ratio from 8.05 to 10.6 GHz (27.34%). A metallic copper cylinder is placed inside the prism to improve the isolation and axial ratio. All the antennas are highly isolated, with isolation is more diminutive than −20.5 dB, except the adjacent element to the edge of the prism, for which it is −14.7 dB. The Envelope Correlation Coefficient (ECC) is less than 0.035. The proposed antenna structure shows the pattern or angle diversity in the whole 360° angle with polarisation diversity.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"10 1","pages":"462 - 474"},"PeriodicalIF":0.0,"publicationDate":"2021-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48639792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An optimised hybrid SOVM modulation based on MDAVT for OEWIM 基于MDAVT的OEWIM优化混合SOVM调制
International Journal of Electronics Letters Pub Date : 2021-11-09 DOI: 10.1080/21681724.2021.2001846
Sriharibabu Avvaru, Sinivasa Rao Gorantla
{"title":"An optimised hybrid SOVM modulation based on MDAVT for OEWIM","authors":"Sriharibabu Avvaru, Sinivasa Rao Gorantla","doi":"10.1080/21681724.2021.2001846","DOIUrl":"https://doi.org/10.1080/21681724.2021.2001846","url":null,"abstract":"ABSTRACT This paper presents a new optimised hybrid space opposite vector modulation (SOVM) strategy based on the multiple division of active vector time (MDAVT) for a dual inverter-fed open-end winding induction motor (OEWIM) to reduce the common mode voltage (CMV) and line current harmonic distortion. Mostly, all the PWM converters yield CMV across the load terminals, which, in turn, results in common mode currents. These common mode currents lead to the failure of bearings in the case of motor loads. In order to reduce this CMV in this paper, a SOVM strategy is adapted. The concept of an optimised MDAVT is also introduced along with the SOVM to obtain the less current ripple. Finally, these adaptions lead to an optimised hybrid PWM strategy and are employed for dual two-level inverter-fed OEWIM. In the present work, to evaluate the optimistic performance of the proposed switching strategy for OEWIM, MATLAB software is chosen. To validate the proposed strategy experimentally, dSPACE 1104 is employed for digital implementation of PWM signals. The superiority of the proposed PWM in terms of CMV is presented with the detailed analysis. However, the superiority in terms of current THD is shown with the help of the simulation and experimental results.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"10 1","pages":"447 - 461"},"PeriodicalIF":0.0,"publicationDate":"2021-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46523101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 261mV Bandgap reference based on Beta Multiplier with 64ppm/0C temp coefficient 基于64ppm/0C温度系数的Beta倍增器的261mV带隙参考
International Journal of Electronics Letters Pub Date : 2021-10-06 DOI: 10.1080/21681724.2021.1966656
R. Nagulapalli, N. Yassine, S. Barker, P. Georgiou, K. Hayatleh
{"title":"A 261mV Bandgap reference based on Beta Multiplier with 64ppm/0C temp coefficient","authors":"R. Nagulapalli, N. Yassine, S. Barker, P. Georgiou, K. Hayatleh","doi":"10.1080/21681724.2021.1966656","DOIUrl":"https://doi.org/10.1080/21681724.2021.1966656","url":null,"abstract":"ABSTRACT In this paper, a low voltage bandgap reference circuit has been proposed. The introduction of a modified beta multiplier bias circuit decreased the mismatch caused by the PMOS transistors opamp contribution. By shifting the fixed resistors to the NMOSs drain side, the beta multiplier bias minimised threshold mismatch between the two NMOS transistors. A 200-point MC simulation showed a 0.9 mV standard deviation, with a 0.34% accuracy. The simulated temperature coefficient was 64 ppm/0C. The proposed circuit consumed 5.04 µW of power from a 0.45 V power supply voltage. A prototype was implemented in 65 nm CMOS technology occupying a 2888 µm2 silicon area, with the nominal value of the reference at 261 mV.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"10 1","pages":"403 - 413"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45174897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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