R. Nagulapalli, N. Yassine, S. Barker, P. Georgiou, K. Hayatleh
{"title":"A 261mV Bandgap reference based on Beta Multiplier with 64ppm/0C temp coefficient","authors":"R. Nagulapalli, N. Yassine, S. Barker, P. Georgiou, K. Hayatleh","doi":"10.1080/21681724.2021.1966656","DOIUrl":null,"url":null,"abstract":"ABSTRACT In this paper, a low voltage bandgap reference circuit has been proposed. The introduction of a modified beta multiplier bias circuit decreased the mismatch caused by the PMOS transistors opamp contribution. By shifting the fixed resistors to the NMOSs drain side, the beta multiplier bias minimised threshold mismatch between the two NMOS transistors. A 200-point MC simulation showed a 0.9 mV standard deviation, with a 0.34% accuracy. The simulated temperature coefficient was 64 ppm/0C. The proposed circuit consumed 5.04 µW of power from a 0.45 V power supply voltage. A prototype was implemented in 65 nm CMOS technology occupying a 2888 µm2 silicon area, with the nominal value of the reference at 261 mV.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"10 1","pages":"403 - 413"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Electronics Letters","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1080/21681724.2021.1966656","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"Engineering","Score":null,"Total":0}
引用次数: 10
Abstract
ABSTRACT In this paper, a low voltage bandgap reference circuit has been proposed. The introduction of a modified beta multiplier bias circuit decreased the mismatch caused by the PMOS transistors opamp contribution. By shifting the fixed resistors to the NMOSs drain side, the beta multiplier bias minimised threshold mismatch between the two NMOS transistors. A 200-point MC simulation showed a 0.9 mV standard deviation, with a 0.34% accuracy. The simulated temperature coefficient was 64 ppm/0C. The proposed circuit consumed 5.04 µW of power from a 0.45 V power supply voltage. A prototype was implemented in 65 nm CMOS technology occupying a 2888 µm2 silicon area, with the nominal value of the reference at 261 mV.
期刊介绍:
International Journal of Electronics Letters (IJEL) is a world-leading journal dedicated to the rapid dissemination of new concepts and developments across the broad and interdisciplinary field of electronics. The Journal welcomes submissions on all topics in electronics, with specific emphasis on the following areas: • power electronics • embedded systems • semiconductor devices • analogue circuits • digital electronics • microwave and millimetre-wave techniques • wireless and optical communications • sensors • instrumentation • medical electronics Papers should focus on technical applications and developing research at the cutting edge of the discipline. Proposals for special issues are encouraged, and should be discussed with the Editor-in-Chief.