{"title":"FPGA Implementation of Polyphase Digital Down Converter for WiMAX Systems","authors":"Debarshi Datta, H. Dutta","doi":"10.1080/21681724.2022.2068659","DOIUrl":null,"url":null,"abstract":"ABSTRACT This paper briefs the implementation of a reconfigurable digital down converter (DDC) on a field-programmablegate array (FPGA) development board to be used in worldwide interoperability for microwave access (WiMAX) applications. The proposed polyphase design includes a parallel number of coordinate rotation digital computer (CORDIC) processors and low-passfinite impulse response (FIR) filters. Furthermore, the single rate FIR filter works with complex data input using canonical implementation. This strategy reduces multiplications and computational complexity. Additionally, the sample rate factor can be dynamically reconfigured to support multistandard DDC architectures. The mathematical expressions of the proposed design are briefly described. Comparison results indicate that the proposed design saves the hardware resources to achieve a cost-effectivesolution for software-definedradio standards. The simulation and experimental results are used to verify the correctness and feasibility of the polyphase DDC structure.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"232 - 240"},"PeriodicalIF":0.0000,"publicationDate":"2022-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Electronics Letters","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1080/21681724.2022.2068659","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"Engineering","Score":null,"Total":0}
引用次数: 1
Abstract
ABSTRACT This paper briefs the implementation of a reconfigurable digital down converter (DDC) on a field-programmablegate array (FPGA) development board to be used in worldwide interoperability for microwave access (WiMAX) applications. The proposed polyphase design includes a parallel number of coordinate rotation digital computer (CORDIC) processors and low-passfinite impulse response (FIR) filters. Furthermore, the single rate FIR filter works with complex data input using canonical implementation. This strategy reduces multiplications and computational complexity. Additionally, the sample rate factor can be dynamically reconfigured to support multistandard DDC architectures. The mathematical expressions of the proposed design are briefly described. Comparison results indicate that the proposed design saves the hardware resources to achieve a cost-effectivesolution for software-definedradio standards. The simulation and experimental results are used to verify the correctness and feasibility of the polyphase DDC structure.
期刊介绍:
International Journal of Electronics Letters (IJEL) is a world-leading journal dedicated to the rapid dissemination of new concepts and developments across the broad and interdisciplinary field of electronics. The Journal welcomes submissions on all topics in electronics, with specific emphasis on the following areas: • power electronics • embedded systems • semiconductor devices • analogue circuits • digital electronics • microwave and millimetre-wave techniques • wireless and optical communications • sensors • instrumentation • medical electronics Papers should focus on technical applications and developing research at the cutting edge of the discipline. Proposals for special issues are encouraged, and should be discussed with the Editor-in-Chief.