International Journal of Electronics Letters最新文献

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Simple Computation of Effective Dielectric Constant for a CPW Configuration CPW结构有效介电常数的简单计算
International Journal of Electronics Letters Pub Date : 2022-08-30 DOI: 10.1080/21681724.2022.2118838
A. Banerjee, A. Bandyopadhyay
{"title":"Simple Computation of Effective Dielectric Constant for a CPW Configuration","authors":"A. Banerjee, A. Bandyopadhyay","doi":"10.1080/21681724.2022.2118838","DOIUrl":"https://doi.org/10.1080/21681724.2022.2118838","url":null,"abstract":"ABSTRACT This article presents the design of a simple-expression-based algorithm that may be used for the computation of the effective dielectric constant for a given coplanar waveguide (CPW) structure in microwave applications. The design is based on multidimensional surface fitting approach. The choice of this expression is justified using a computed/simulated dataset. A very simple intuitive method is developed for this purpose. Simple expressions are defined repetitively to compute the previous relevant parameters. The coefficients of the expressions are calculated based on their dependency over the physical attributes of the structure concerned.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41340494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Multiband Frequency Reconfigurable and Bifunctional Metasurface 一种多频带可重构双功能元表面
International Journal of Electronics Letters Pub Date : 2022-08-29 DOI: 10.1080/21681724.2022.2118841
B. Anil Babu, B. Madhav, K. Srilatha, M. Rao, Sudipta Das
{"title":"A Multiband Frequency Reconfigurable and Bifunctional Metasurface","authors":"B. Anil Babu, B. Madhav, K. Srilatha, M. Rao, Sudipta Das","doi":"10.1080/21681724.2022.2118841","DOIUrl":"https://doi.org/10.1080/21681724.2022.2118841","url":null,"abstract":"ABSTRACT A multiband, frequency reconfigurable, and bifunctional metasurface for simultaneous full-space control of Electromagnetic (EM) waves is proposed for wearable applications. The unit-cell structure contains concentric rectangular rings and empty substrate-integrated waveguides (SIWs) for miniaturisation. The miniaturised dimension of the Polydimethylsiloxane (PDMS) substrate is 18 × 18 × 1 mm3. Two varactor diodes are integrated for frequency switching operations by configuring the structure using bias voltage (forward/reverse) through the ground via the proposed surface resonates at 3.5,5.8,7.6 (On),8.1 (Off) GHz frequencies, which provide simultaneous bi-functionalities: artificial Magnetic Conductor (AMC) reflector/absorber in reflection and transmission space of operations, respectively. In reflection space, it acts as an AMC reflector by providing in-phase reflection with a radiation efficiency of >84% and unidirectional E-field patterns. However, the magnitude of absorbance is more than 96% in transmission, thereby simultaneously controlling full-space EM wave in normal incidence. The obtained simultaneous metasurface functionalities are investigated for different oblique angles of the transverse electric (TE) and transverse magnetic (TM) incident wave. The proposed surface is fabricated and experimentally validated. The features of the designed bifunctional metasurface provide a strategic platform for potential multifunctional wearable devices.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45325634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Frequency Response Analysis of CNT Bundle Interconnects CNT束互连的频率响应分析
International Journal of Electronics Letters Pub Date : 2022-08-26 DOI: 10.1080/21681724.2022.2117849
M. Shefali, K. Fatima, P. Uma Sathyakam
{"title":"Frequency Response Analysis of CNT Bundle Interconnects","authors":"M. Shefali, K. Fatima, P. Uma Sathyakam","doi":"10.1080/21681724.2022.2117849","DOIUrl":"https://doi.org/10.1080/21681724.2022.2117849","url":null,"abstract":"ABSTRACT When carbon nanotubes (CNTs) are used in interconnects, their electrical properties are appealing as they are not affected by surface scattering when the feature size decreases. After almost two decades of research on CNT-based interconnects, it is still a question which type of CNT bundle performs better than the other. There are many contradictory reports in this regard. So, it is very important to study the frequency response of these interconnects to ascertain their actual performance and compare them. HSPICE-based circuit simulations at 20 nm and 14 nm technology nodes are carried out. Furthermore, the analysis for local, semi-global and global interconnect lengths is carried out. Results show that single-walled CNT (SWCNT) bundles have higher voltage gain and higher current gain for all lengths at both the technology nodes. These results are significant in understanding the best choice of interconnects among SWCNT bundle, MWCNT bundle and mixed CNT bundle interconnects.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45591390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modified Priority Encoder based Hardware Efficient N-bit Comparator 基于改进优先级编码器的硬件高效N位比较器
International Journal of Electronics Letters Pub Date : 2022-08-25 DOI: 10.1080/21681724.2022.2117848
Nalini Bodasingi, Krishnateja Varasala, Srinivasu Saladi, Appala Naidu Chalumuri, B. Jammu, S. Veeramachaneni
{"title":"Modified Priority Encoder based Hardware Efficient N-bit Comparator","authors":"Nalini Bodasingi, Krishnateja Varasala, Srinivasu Saladi, Appala Naidu Chalumuri, B. Jammu, S. Veeramachaneni","doi":"10.1080/21681724.2022.2117848","DOIUrl":"https://doi.org/10.1080/21681724.2022.2117848","url":null,"abstract":"ABSTRACT Digital Circuits applications are expanding rapidly in modern times because they generate correct signals without errors or interferences. These digital circuits play important roles in data storage operation, as well as the implementation of image processing applications on hardware where the power, speed, and area of an electronic device play a significant role, particularly in the field of modern VLSI technology. The digital comparator with more number of bits plays an important role in image processing applications. In the proposed research paper, an attempt is made to design a speed and area efficient 32-bit comparator. To improve the speed of the comparator a modified priority encoder technique is used. It shows that the area of proposed 32-bit digital comparator consumes 573.73 units which are 20% better than when compared with the conventional comparators and the speed improved by 50% when compared with the Conventional Comparators. The proposed implementation is simulated on the ‘Encounter(R) RTL Compiler RC14.28’.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48019240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 100-MHz 3.352-mW 8-bit shift register using low-power DETFF using 90-nm CMOS process 使用90nm CMOS工艺的低功耗DETFF的100MHz 3.352-mW 8位移位寄存器
International Journal of Electronics Letters Pub Date : 2022-06-23 DOI: 10.1080/21681724.2022.2087912
Chua-Chin Wang, L. K. Tolentino, Uday Kiran Naidu Ekkurthi, Pang-Yen Lou, S. Sampath
{"title":"A 100-MHz 3.352-mW 8-bit shift register using low-power DETFF using 90-nm CMOS process","authors":"Chua-Chin Wang, L. K. Tolentino, Uday Kiran Naidu Ekkurthi, Pang-Yen Lou, S. Sampath","doi":"10.1080/21681724.2022.2087912","DOIUrl":"https://doi.org/10.1080/21681724.2022.2087912","url":null,"abstract":"ABSTRACT By keeping the very same transmission rate, a scheme is provided by DETFF (double-edge triggered flip-flops) for power dissipation reduction. As a result, they are suitable for use as shift registers. This investigation discussed various previous DETFF designs and demonstrated a new DETFF circuit applied to construct an 8-bit low-power shift register. This study makes a significant contribution by using two parallel data paths that operate in a single clock’s opposing phases where an inverted input trigger is unnecessary. TSMC 90-nm complementary metal-oxide semiconductor (CMOS) technology was used to implement the proposed shift register. Comparing the proposed DETFF with prior works, it has fewer transistor counts since the negated input trigger and auxiliary devices were removed, resulting in lower area cost and lower power dissipation. At 100 MHz clock frequency and lower supply voltage of 1.0 V, it demonstrates a power consumption of 3.352 mW on silicon, making it suitable for low-power applications. Lastly, it has the best performance compared with prior works speaking of larger scale, as demonstrated by the chip’s functionality and jitter measurement at the maximum frequency of 200 MHz.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"300 - 315"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46970082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Kronecker Product Based Modeling of Darlington Amplifier and State Estimation using Unscented Kalman Filter 基于Kronecker积的达林顿放大器建模及无气味卡尔曼滤波状态估计
International Journal of Electronics Letters Pub Date : 2022-06-21 DOI: 10.1080/21681724.2022.2087916
A. Gautam, Sudipta Majumdar
{"title":"Kronecker Product Based Modeling of Darlington Amplifier and State Estimation using Unscented Kalman Filter","authors":"A. Gautam, Sudipta Majumdar","doi":"10.1080/21681724.2022.2087916","DOIUrl":"https://doi.org/10.1080/21681724.2022.2087916","url":null,"abstract":"ABSTRACT This paper presents the application of unscented Kalman filter (UKF) for output voltage estimation of the Darlington amplifier (DA). Implementation of UKF requires the state-space model of DA circuit, which has been obtained using Kirchhoff’s voltage law (KVL), Kirchhoff’s current law (KCL) and the Gummel–Poon model of the bipolar junction transistor (BJT). This work uses Kronecker product for vector multiplication. The mathematical representation of nonlinear system in terms of Kronecker product helps to reduce the computational burden involved in the vector multiplication. The proposed method has the advantage that it can be used for the nonlinear region and large amplitude input signal. As the maximal precision of estimation requires modelling in terms of circuit elements and device parameters, the proposed method is able to provide an accurate estimation. We compared the UKF estimation results with the extended Kalman filter (EKF) and iterated extended Kalman filter (IEKF). The UKF presents smaller mean square error (MSE) as compared to EKF and IEKF as UKF is accurate to the third order for any nonlinearity. In addition, IEKF presents smaller MSE as compared to EKF because the linearisation error is taken into account by IEKF.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48229308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance investigation of Ge DLTFET based digital integrated circuit 基于Ge-DLTFET的数字集成电路性能研究
International Journal of Electronics Letters Pub Date : 2022-06-20 DOI: 10.1080/21681724.2022.2087914
Prashant Kumar, Meena Panchore, P. Raikwal, Kanchan Cecil
{"title":"Performance investigation of Ge DLTFET based digital integrated circuit","authors":"Prashant Kumar, Meena Panchore, P. Raikwal, Kanchan Cecil","doi":"10.1080/21681724.2022.2087914","DOIUrl":"https://doi.org/10.1080/21681724.2022.2087914","url":null,"abstract":"ABSTRACT The article investigates the performance of germanium source doping-less tunnel FET (Ge DLTFET)-based digital integrated circuits. For this, the compact models have been developed for DLTFETs using Verilog-A approach. Furthermore, at circuit level, the performance of Ge DLTFET is compared with its conventional counterpart silicon source DLTFET (Si DLTEFT). Two digital benchmark circuits are considered for circuit simulation such as ring oscillator (RO) and conventional six-transistor static random-access memory (6 T SRAM). The simulation results depict that the operating frequency of Ge DLTFET RO is ~ 4.48 decade higher than Si DLTFET. Similarly, the performance of Ge DLTFET SRAM cell in terms of read and write delay is much better than its conventional counterpart Si DLTFET. Hence, Ge DLTFET can be considered as a promising device structure for high-speed digital circuit design and for its applications.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"339 - 345"},"PeriodicalIF":0.0,"publicationDate":"2022-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49618793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Numerical model & design of wideband band reject filter with closed loop rectangular resonator 闭环矩形谐振宽带带阻滤波器的数值模型与设计
International Journal of Electronics Letters Pub Date : 2022-06-09 DOI: 10.1080/21681724.2022.2087910
N. Kumari, M. Sood, S. Talluri, S. Khah
{"title":"Numerical model & design of wideband band reject filter with closed loop rectangular resonator","authors":"N. Kumari, M. Sood, S. Talluri, S. Khah","doi":"10.1080/21681724.2022.2087910","DOIUrl":"https://doi.org/10.1080/21681724.2022.2087910","url":null,"abstract":"ABSTRACT Numerical model of a wideband band reject filter using closed rectangular loop resonator is presented using transmission lines. The prototype design of wide band reject filter centred at 3 GHz with lower cut-off frequency of 2 GHz and upper cut-off frequency of 4 GHz is fabricate from the optimal values obtained from the numeric model on a substrate (FR4) with a dielectric constant of 4.3, loss tangent of 0.02–0.03 and substrate height of 1.6 mm. For bidirectional operations, the length-to-width ratio of filter is 2:1. The impedance of the transmission line which is connected between input and output ports is taken as double the feed line impedance while the impedance of the other half wavelength is considered as four times the feed line impedance. The design has obtained bandwidth of more than 60%. It is observed that the full wave electromagnetic results are in good agreement with the experimental and numerical results.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"281 - 290"},"PeriodicalIF":0.0,"publicationDate":"2022-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47329541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High linear low voltage CMOS power amplifier for 2.4 GHz applications 适用于2.4GHz应用的高线性低压CMOS功率放大器
International Journal of Electronics Letters Pub Date : 2022-06-09 DOI: 10.1080/21681724.2022.2087915
S. Manjula, P. Anandan, M. Suganthy
{"title":"High linear low voltage CMOS power amplifier for 2.4 GHz applications","authors":"S. Manjula, P. Anandan, M. Suganthy","doi":"10.1080/21681724.2022.2087915","DOIUrl":"https://doi.org/10.1080/21681724.2022.2087915","url":null,"abstract":"ABSTRACT Wireless technology is a growing technology in which lot of attention move towards 2.4 GHz frequency applications. In transceiver front end, power amplifier is an important block of a transmitter. A low voltage power amplifier is proposed using 0.13 µm TSMC CMOS process. In this proposed work, single-ended two stage class AB power amplifier is designed and RF distortion technique is applied to improve linearity. The high linearity low voltage power amplifier is designed and simulated using ADS simulator. The optimised power amplifier produces 18 dB gain, 21.6% PAE, 21.7 dBm of OIP3 and 5.86 mA current consumption at 0.8 V supply voltage.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"346 - 354"},"PeriodicalIF":0.0,"publicationDate":"2022-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43452005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MIMO-OFDM channel estimation based on minimum error entropy criterion under non-Gaussian environment 非高斯环境下基于最小误差熵准则的MIMO-OFDM信道估计
International Journal of Electronics Letters Pub Date : 2022-06-09 DOI: 10.1080/21681724.2022.2087909
Arash Soltani, Mehdi Airamlozadeh, Jaber Parchami
{"title":"MIMO-OFDM channel estimation based on minimum error entropy criterion under non-Gaussian environment","authors":"Arash Soltani, Mehdi Airamlozadeh, Jaber Parchami","doi":"10.1080/21681724.2022.2087909","DOIUrl":"https://doi.org/10.1080/21681724.2022.2087909","url":null,"abstract":"ABSTRACT Using the orthogonal frequency division multiplexing (OFDM) technique, a multiple-input multiple-output (MIMO) system can provide high spectral efficiency and high data transmission over a fading channel. To achieve the best performance in a MIMO-OFDM system, high accuracy in channel estimation is a very important factor which leads to appropriate receiver design. Therefore, in the most channel estimation algorithms, the mean square error (MSE) is the main criterion for noise minimisation which is robust in the case of Gaussian noise. However, in telecommunication systems which do not have noise with Gaussian distribution, the MSE criterion is not appropriate. So as to tackle this problem, a robust adaptive filtering algorithm was proposed using minimum error entropy (MEE) criterion and improved least square (ILS) approach which by far is better than MMSE criterion to robust channel estimation. In this work, impulsive noise is used for non-Gaussian environment simulation. Furthermore, MEE is employed to attenuate the impulsive noise, and ILS is adopted to reduce LS estimation variance. Compared to the MSE-based algorithms, simulation results indicate that the proposed method outperforms the channel estimation in a non-Gaussian environment.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"267 - 280"},"PeriodicalIF":0.0,"publicationDate":"2022-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43931881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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