基于Ge-DLTFET的数字集成电路性能研究

Q3 Engineering
Prashant Kumar, Meena Panchore, P. Raikwal, Kanchan Cecil
{"title":"基于Ge-DLTFET的数字集成电路性能研究","authors":"Prashant Kumar, Meena Panchore, P. Raikwal, Kanchan Cecil","doi":"10.1080/21681724.2022.2087914","DOIUrl":null,"url":null,"abstract":"ABSTRACT The article investigates the performance of germanium source doping-less tunnel FET (Ge DLTFET)-based digital integrated circuits. For this, the compact models have been developed for DLTFETs using Verilog-A approach. Furthermore, at circuit level, the performance of Ge DLTFET is compared with its conventional counterpart silicon source DLTFET (Si DLTEFT). Two digital benchmark circuits are considered for circuit simulation such as ring oscillator (RO) and conventional six-transistor static random-access memory (6 T SRAM). The simulation results depict that the operating frequency of Ge DLTFET RO is ~ 4.48 decade higher than Si DLTFET. Similarly, the performance of Ge DLTFET SRAM cell in terms of read and write delay is much better than its conventional counterpart Si DLTFET. Hence, Ge DLTFET can be considered as a promising device structure for high-speed digital circuit design and for its applications.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":"11 1","pages":"339 - 345"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Performance investigation of Ge DLTFET based digital integrated circuit\",\"authors\":\"Prashant Kumar, Meena Panchore, P. Raikwal, Kanchan Cecil\",\"doi\":\"10.1080/21681724.2022.2087914\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"ABSTRACT The article investigates the performance of germanium source doping-less tunnel FET (Ge DLTFET)-based digital integrated circuits. For this, the compact models have been developed for DLTFETs using Verilog-A approach. Furthermore, at circuit level, the performance of Ge DLTFET is compared with its conventional counterpart silicon source DLTFET (Si DLTEFT). Two digital benchmark circuits are considered for circuit simulation such as ring oscillator (RO) and conventional six-transistor static random-access memory (6 T SRAM). The simulation results depict that the operating frequency of Ge DLTFET RO is ~ 4.48 decade higher than Si DLTFET. Similarly, the performance of Ge DLTFET SRAM cell in terms of read and write delay is much better than its conventional counterpart Si DLTFET. Hence, Ge DLTFET can be considered as a promising device structure for high-speed digital circuit design and for its applications.\",\"PeriodicalId\":13968,\"journal\":{\"name\":\"International Journal of Electronics Letters\",\"volume\":\"11 1\",\"pages\":\"339 - 345\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Journal of Electronics Letters\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1080/21681724.2022.2087914\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"Engineering\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Electronics Letters","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1080/21681724.2022.2087914","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"Engineering","Score":null,"Total":0}
引用次数: 0

摘要

本文研究了基于锗源掺杂少隧道FET(Ge-DLTFET)的数字集成电路的性能。为此,使用Verilog-A方法为DLTFET开发了紧凑型模型。此外,在电路水平上,将Ge DLTFET的性能与其传统的对应硅源DLTFET(Si DLTEFT)进行了比较。考虑了两种数字基准电路进行电路仿真,如环形振荡器(RO)和传统的六晶体管静态随机存取存储器(6T SRAM)。仿真结果表明,Ge DLTFET RO的工作频率比Si DLTFET高约4.48倍。类似地,Ge DLTFET SRAM单元在读取和写入延迟方面的性能比其传统的对应物Si DLTFET要好得多。因此,Ge DLTFET可以被认为是一种很有前途的高速数字电路设计及其应用的器件结构。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Performance investigation of Ge DLTFET based digital integrated circuit
ABSTRACT The article investigates the performance of germanium source doping-less tunnel FET (Ge DLTFET)-based digital integrated circuits. For this, the compact models have been developed for DLTFETs using Verilog-A approach. Furthermore, at circuit level, the performance of Ge DLTFET is compared with its conventional counterpart silicon source DLTFET (Si DLTEFT). Two digital benchmark circuits are considered for circuit simulation such as ring oscillator (RO) and conventional six-transistor static random-access memory (6 T SRAM). The simulation results depict that the operating frequency of Ge DLTFET RO is ~ 4.48 decade higher than Si DLTFET. Similarly, the performance of Ge DLTFET SRAM cell in terms of read and write delay is much better than its conventional counterpart Si DLTFET. Hence, Ge DLTFET can be considered as a promising device structure for high-speed digital circuit design and for its applications.
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来源期刊
International Journal of Electronics Letters
International Journal of Electronics Letters Engineering-Electrical and Electronic Engineering
CiteScore
1.80
自引率
0.00%
发文量
42
期刊介绍: International Journal of Electronics Letters (IJEL) is a world-leading journal dedicated to the rapid dissemination of new concepts and developments across the broad and interdisciplinary field of electronics. The Journal welcomes submissions on all topics in electronics, with specific emphasis on the following areas: • power electronics • embedded systems • semiconductor devices • analogue circuits • digital electronics • microwave and millimetre-wave techniques • wireless and optical communications • sensors • instrumentation • medical electronics Papers should focus on technical applications and developing research at the cutting edge of the discipline. Proposals for special issues are encouraged, and should be discussed with the Editor-in-Chief.
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