International Journal of Electronics Letters最新文献

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Synthesis of memristive one-ports with piecewise-smooth characteristics 具有分段平滑特性的忆阻单端口的合成
International Journal of Electronics Letters Pub Date : 2022-11-17 DOI: 10.1080/21681724.2022.2148286
V. Semenov
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引用次数: 1
New Tunable Phase Oscillator Structure 新型可调谐相位振荡器结构
International Journal of Electronics Letters Pub Date : 2022-11-16 DOI: 10.1080/21681724.2022.2148284
A. Elwakil, C. Psychalinos, B. Maundy
{"title":"New Tunable Phase Oscillator Structure","authors":"A. Elwakil, C. Psychalinos, B. Maundy","doi":"10.1080/21681724.2022.2148284","DOIUrl":"https://doi.org/10.1080/21681724.2022.2148284","url":null,"abstract":"","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43219228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of low profile, compact, high gain and broadband metasurface-based MIMO antenna for 5G/WiMAX/WLAN applications 用于5G/WiMAX/WLAN应用的低轮廓、紧凑、高增益和宽带元表面MIMO天线的设计
International Journal of Electronics Letters Pub Date : 2022-11-15 DOI: 10.1080/21681724.2022.2148285
Kaushal Vala, S. Hadia
{"title":"Design of low profile, compact, high gain and broadband metasurface-based MIMO antenna for 5G/WiMAX/WLAN applications","authors":"Kaushal Vala, S. Hadia","doi":"10.1080/21681724.2022.2148285","DOIUrl":"https://doi.org/10.1080/21681724.2022.2148285","url":null,"abstract":"","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43643317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-stage switched-inductor switched-capacitor high gain DC-DC converter 多级开关电感开关电容高增益DC-DC转换器
International Journal of Electronics Letters Pub Date : 2022-11-09 DOI: 10.1080/21681724.2022.2140835
M. Dwivedi, J. R
{"title":"Multi-stage switched-inductor switched-capacitor high gain DC-DC converter","authors":"M. Dwivedi, J. R","doi":"10.1080/21681724.2022.2140835","DOIUrl":"https://doi.org/10.1080/21681724.2022.2140835","url":null,"abstract":"ABSTRACT This paper presents a Multi-stage Switch Inductor Switch Capacitor High Gain DC-DC Converter for microgrid application designed with integrated Active Switch Capacitor (ASC) and Active Passive Inductor Cell (APIC). The closed loop control of a proposed voltage lift DC-DC converter is performed to ensure the constant output voltage disregarding the change in input voltage. The new high gain extendable DC-DC boost converter topology is capable of providing high-gain voltage with low duty cycle and it is extendable by increasing the number of APIC network. Analytical modelling of the proposed converter is carried out to obtain the technical specifications. The open loop and closed loop simulation model of the proposed converter is developed in the MATLAB/Simulink environment to analyse the performance of the converter. The microcontroller-based hardware model of the proposed converter of power rated 200 W (18/200 V at 50% duty ratio) is developed and tested in open loop to validate the simulation results and experimental set-up results are reported.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49344515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Simulation Based Analysis of Low-Voltage-Tunable Biquad Filter Using Operational Transconductance Amplifiers 基于运算跨导放大器的低压可调谐双路滤波器仿真分析
International Journal of Electronics Letters Pub Date : 2022-10-03 DOI: 10.1080/21681724.2022.2129808
Anamika Raj, Sangeeta Singh, Pankaj Kumar
{"title":"Simulation Based Analysis of Low-Voltage-Tunable Biquad Filter Using Operational Transconductance Amplifiers","authors":"Anamika Raj, Sangeeta Singh, Pankaj Kumar","doi":"10.1080/21681724.2022.2129808","DOIUrl":"https://doi.org/10.1080/21681724.2022.2129808","url":null,"abstract":"","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46050961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance Analysis of Multi User MIMO NOMA Network with Hierarchical Clustering 基于层次聚类的多用户MIMO NOMA网络性能分析
International Journal of Electronics Letters Pub Date : 2022-09-27 DOI: 10.1080/21681724.2022.2129810
Aradhana Misra, Udit Ranjan Kalita, K. K. Sarma
{"title":"Performance Analysis of Multi User MIMO NOMA Network with Hierarchical Clustering","authors":"Aradhana Misra, Udit Ranjan Kalita, K. K. Sarma","doi":"10.1080/21681724.2022.2129810","DOIUrl":"https://doi.org/10.1080/21681724.2022.2129810","url":null,"abstract":"","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42350884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
20 GHz Substrate Crosstalk Sensor for Mobile Communication Applications 用于移动通信应用的20ghz基板串扰传感器
International Journal of Electronics Letters Pub Date : 2022-09-27 DOI: 10.1080/21681724.2022.2129807
K. Moustakas, T. Noulis, S. Siskos
{"title":"20 GHz Substrate Crosstalk Sensor for Mobile Communication Applications","authors":"K. Moustakas, T. Noulis, S. Siskos","doi":"10.1080/21681724.2022.2129807","DOIUrl":"https://doi.org/10.1080/21681724.2022.2129807","url":null,"abstract":"","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43533334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reduction of PAPR in OTFS using rooting companding techniques 利用生根压扩技术降低OTFS中的PAPR
International Journal of Electronics Letters Pub Date : 2022-09-07 DOI: 10.1080/21681724.2022.2118839
Hanumantharao Bitra, P. Ponnusamy, S. Chintagunta
{"title":"Reduction of PAPR in OTFS using rooting companding techniques","authors":"Hanumantharao Bitra, P. Ponnusamy, S. Chintagunta","doi":"10.1080/21681724.2022.2118839","DOIUrl":"https://doi.org/10.1080/21681724.2022.2118839","url":null,"abstract":"ABSTRACT Peak-to-average power ratio (PAPR) is one of the major limitations of an orthogonal time frequency space (OTFS) system. To reduce the PAPR, this paper proposes three companding techniques, namely, logarithmic rooting companding, rooting companding, and rooting-based -law companding. This paper also presents the preferable range of rooting parameter through the analysis of variation of PAPR and bit error rate (BER) with respect to the rooting parameter. To assess the performance of the proposed companding techniques, simulations are carried out by considering various number of delay and Doppler bins. The simulation results reveal that all the proposed techniques provide better PAPR performance than the existing -law companding.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43221023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Performance Analysis of Multihop Wireless Systems with Decode and Forward Relays over Fisher- Snedecor F Fading Channels Fisher-Snedecor F衰落信道下具有解码和前向中继的多跳无线系统的性能分析
International Journal of Electronics Letters Pub Date : 2022-08-30 DOI: 10.1080/21681724.2022.2118840
Rajkishur Mudoi
{"title":"Performance Analysis of Multihop Wireless Systems with Decode and Forward Relays over Fisher- Snedecor F Fading Channels","authors":"Rajkishur Mudoi","doi":"10.1080/21681724.2022.2118840","DOIUrl":"https://doi.org/10.1080/21681724.2022.2118840","url":null,"abstract":"ABSTRACT By reducing the transmitting power at the base station and expanding the coverage range of wireless communication, cooperative communication has turned into a higher imperative. This article evaluates the outage probability, average symbol error rate (ASER) for coherent as well as noncoherent modulation pattern, ergodic capacity and throughput of a multihop communication technique over the Fisher–Snedecor F fading channels. The multihop transmission scheme utilises a source, a set of relays and the destination node. The intervening relays of the system are regenerative with decode and forward type. Each hop of the system undergoes Fisher–Snedecor F fading channels. The MGF-based approach is used to derive the ASER of the system. The outage probability and ASER performance upgrade with the advancement of fading parameter as well as shadowing parameter of the channel. The ergodic capacity decreases with the improvement in shadowing parameter and the number of hops. The throughput of the system rises in connection with the reduction of total hops. Simulations validate the correctness of the numerically appraised results.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41456628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 10-Gbps CTLE Design Using Split-Length Input Pair MOS Transistors 一种使用分割长度输入对MOS晶体管的10gbps CTLE设计
International Journal of Electronics Letters Pub Date : 2022-08-30 DOI: 10.1080/21681724.2022.2117850
Ahmed G. Shehata, G. Fahmy, H. Ragai
{"title":"A 10-Gbps CTLE Design Using Split-Length Input Pair MOS Transistors","authors":"Ahmed G. Shehata, G. Fahmy, H. Ragai","doi":"10.1080/21681724.2022.2117850","DOIUrl":"https://doi.org/10.1080/21681724.2022.2117850","url":null,"abstract":"ABSTRACT The equaliser is an indispensable block inside the receiver in Serial Link systems. It is used to moderate the high-frequency loss of the signal in the channel. A new technique is described to improve the performance of the Continuous-Time Linear Equaliser (CTLE). This technique utilises split-length device (SLD) in order to boost the output impedance of the SLD. The proposed CTLE is designed and simulated in 65 nm CMOS technology. Post-layout simulation results demonstrate that the proposed technique has more peaking than conventional CTLE by an order of 1.5 dB at Nyquist frequency. The Proposed design has a vertical eye-opening of 220 mV and a horizontal eye-opening of 0.35 UI. It consumes 1.56 mW from a 1.2 V supply. A FoM of 13.1 fJ/bit/dB is achieved.","PeriodicalId":13968,"journal":{"name":"International Journal of Electronics Letters","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48679023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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