7th International Symposium on Quality Electronic Design (ISQED'06)最新文献_第9页

Using abstraction for efficient formal verification of pipelined processors with value prediction 使用抽象对具有值预测的流水线处理器进行有效的形式化验证

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.142

M. Velev

{"title":"Using abstraction for efficient formal verification of pipelined processors with value prediction","authors":"M. Velev","doi":"10.1109/ISQED.2006.142","DOIUrl":"https://doi.org/10.1109/ISQED.2006.142","url":null,"abstract":"Presented are abstraction techniques that accelerate the formal verification of pipelined processors with value prediction. The formal verification is done by modeling based on the logic of equality with uninterpreted functions and memories (EUFM), and using an automatic tool flow. Applying special abstractions in previous work had resulted in EUFM correctness formulas where most of the terms (abstract word-level values) appear in only positive equations (equality comparisons) or as arguments of uninterpreted functions and uninterpreted predicates, allowing such terms to be treated as distinct constants - a property called positive equality. That property produced orders of magnitude speedup. However, in processors with value prediction, the mechanism for correcting value mispredictions introduces both positive and negated equations between the actual and predicted values, thus reducing significantly the potential for exploiting positive equality. The contributions of this paper are: 1) modeling and formal verification of pipelined processors with load-value prediction and fully implemented mechanism for correcting load-value mispredictions; 2) an approach to abstract the mechanism for detecting load-value mispredictions, thus allowing the use of positive equality, at the cost of enriching the specification processor with the abstracted mechanism for detecting load-value mispredictions; and 3) the observation that this abstraction technique is general and applicable to the formal verification of pipelined processors with other forms of value prediction, e.g., branch prediction, as illustrated with experimental results. The presented abstraction technique produced an order of magnitude speedup when formally verifying a 5-stage pipelined processor with load-value prediction. It can be expected that the speedup would be significantly greater for more complex processors with value prediction","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115004634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A watermarking system for IP protection by buffer insertion technique 基于缓冲区插入技术的IP保护水印系统

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.19

Guangyu Sun, Zhiqiang Gao, Yi Xu

引用次数: 8

Time redundancy based scan flip-flop reuse to reduce SER of combinational logic 基于时间冗余的扫描触发器复用，降低组合逻辑的误码率

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.137

P. Elakkumanan, K. Prasad, R. Sridhar

引用次数: 27

Logic SER reduction through flip flop redesign 通过触发器重新设计来减少逻辑SER

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.82

V. Joshi, Rajeev R. Rao, D. Blaauw, D. Sylvester

引用次数: 46

Post-layout gate sizing for interconnect delay and crosstalk noise optimization 用于互连延迟和串扰噪声优化的布局后栅极尺寸

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.101

N. Hanchate, Nagarajan Ranganathan

{"title":"Post-layout gate sizing for interconnect delay and crosstalk noise optimization","authors":"N. Hanchate, Nagarajan Ranganathan","doi":"10.1109/ISQED.2006.101","DOIUrl":"https://doi.org/10.1109/ISQED.2006.101","url":null,"abstract":"In this paper, we develop a new post-layout gate sizing algorithm for simultaneous optimization of interconnect delay and crosstalk noise. We have modeled the problem of gate sizing as a normal form game and solved using the Nash equilibrium. The noise induced on a net depends on the size of the gates driving the coupled nets and itself. Increasing the gate size of the driver increases the noise induced by the net on its coupled nets, where as, increasing the size of the driver of coupled nets increases the noise induced on the net itself, resulting in a conflicting situation. The problem of post-layout gate size optimization is difficult to solve due to its conflicting nature (M. R. Becer, 2003). Game theory provides a natural framework for handling such conflicting situations and allows multi-metric optimization. We have exploited this property of game theory to solve the cyclic dependency of crosstalk noise on its gate sizes, while modeling the problem of gate sizing for simultaneous optimization of interconnect delay and crosstalk noise, which again are conflicting in nature. Experimental results on several medium and large opencore designs indicate average improvements of 13.33% and 16.61% for interconnect delay and crosstalk noise, without any area overhead or need for re-routing","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121832473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Partial selective encryption: an improved system for protecting VLSI design data in the OASIS format 部分选择性加密:一种用于保护OASIS格式的VLSI设计数据的改进系统

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.98

A. P. Kulkarni, T. J. Grebinski

引用次数: 0

Area efficient temporal coding schemes for reducing crosstalk effects 减少串扰效应的区域有效时间编码方案

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.28

Jean-Marc Philippe, S. Pillement, O. Sentieys

引用次数: 21

Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask 在完全盐化的130纳米CMOS技术中提高ESD稳健性的假门结构，而无需使用额外的盐化阻挡掩模

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.54

Hsin-Chyh Hsu, M. Ker

引用次数: 2

Design of window comparators for integrator-based capacitor array testing circuits 基于积分器的电容阵列测试电路的窗口比较器设计

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.47

A. Laknaur, Haibo Wang

引用次数: 3

Power-aware test pattern generation for improved concurrency at the core level 功率感知测试模式生成，以改进核心层的并发性

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.104

Arkan Abdulrahman, S. Tragoudas

引用次数: 0