Design of window comparators for integrator-based capacitor array testing circuits

Abstract

This paper investigates the impact of window comparator threshold variations on the performance of integrator-based programmable capacitor array (PCA) testing circuits. It presents two window comparator designs that take different approaches to address the problem of comparator threshold variations in PCA testing. The first comparator design utilizes a fully symmetric circuit structure to achieve small threshold deviations. The second design relies on increasing testing time to reduce the effect of comparator threshold variations. Experimental results are presented to compare the performance of the two design approaches