7th International Symposium on Quality Electronic Design (ISQED'06)最新文献

Delay fault diagnosis for nonrobust test 非鲁棒试验延迟故障诊断

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.45

V. Mehta, M. Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, J. Rajski

引用次数: 12

Variational interconnect delay metrics for statistical timing analysis 用于统计时序分析的变分互连延迟度量

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.143

P. Ghanta, S. Vrudhula

{"title":"Variational interconnect delay metrics for statistical timing analysis","authors":"P. Ghanta, S. Vrudhula","doi":"10.1109/ISQED.2006.143","DOIUrl":"https://doi.org/10.1109/ISQED.2006.143","url":null,"abstract":"For statistical timing analysis and physical design optimization, interconnect delay metrics that model the delay as a function of the metal process variations are very important. Accurate linear or at most second order delay models in terms of the process variables are necessary to efficiently propagate uncertainty in the state-of-the-art VLSI designs with millions of transistors and on chip interconnects. In this paper, we develop a method to extend the traditional moment based delay analysis of interconnects to consider the impact of Gaussian metal process variations and obtain mean-square optimal linear delay models for interconnects. We consider linear models for the variations in the conductance and capacitance of interconnects and represent the moments (m0, m1, m2) of the interconnect impulse response as a first order orthogonal polynomial series expansion in the process variables. We obtain the coefficients of the expansion by using the Galerkin residual error minimization method on the recursive equations that relate the interconnect moments (m0, m1 , m2). We compare the accuracy of our approach against SPICE based Monte Carlo simulations and demonstrate a good match","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123132378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Fast sequential cell noise immunity characterization using meta-stable point of feedback loop 基于反馈回路亚稳定点的快速序列细胞抗噪特性研究

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.67

N. Oh, Li Ding, Alireza Kasnavi

引用次数: 4

Minimizing FPGA reconfiguration data at logic level 最小化FPGA在逻辑级的重构数据

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.87

K. Raghuraman, Haibo Wang, S. Tragoudas

引用次数: 4

Enhancement of signal integrity and power integrity with embedded capacitors in high-speed packages 高速封装中嵌入电容增强信号完整性和功率完整性

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.60

K. Srinivasan, P. Muthana, R. Mandrekar, E. Engin, Jinwoo Choi, M. Swaminathan

{"title":"Enhancement of signal integrity and power integrity with embedded capacitors in high-speed packages","authors":"K. Srinivasan, P. Muthana, R. Mandrekar, E. Engin, Jinwoo Choi, M. Swaminathan","doi":"10.1109/ISQED.2006.60","DOIUrl":"https://doi.org/10.1109/ISQED.2006.60","url":null,"abstract":"Improvements in electrical performance of microelectronic systems can be achieved by the integration of passive elements such as capacitors, resistors and inductors. The advantage of embedded passives is their low parasitic values. In this paper, enhancement of signal-integrity and power-integrity is investigated when a high-k planar capacitor is used as a power-ground plane, with embedded high-k discrete capacitors that have low ESI and ESR values as decoupling capacitors for SSN suppression. In order to capture the effects of embedded capacitor performance, a test-structure involving many signal-lines referenced to a power-ground plane was simulated. Simulation results show that the high-k planar capacitor reduces coupling of noise currents through the power-ground planes and helps improve the eye-opening. Simulation results have been quantified for a case, where a fewer number of embedded discrete capacitors helps reduce SSN more significantly than surface-mounts. Transient co-simulation of the signal delivery network (SDN) and the power-delivery network (PDN) are performed using Y-parameters","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127258126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Impact of gate-length biasing on threshold-voltage selection 门长偏置对阈值电压选择的影响

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.72

A. Kahng, S. Muddu, P. Sharma

{"title":"Impact of gate-length biasing on threshold-voltage selection","authors":"A. Kahng, S. Muddu, P. Sharma","doi":"10.1109/ISQED.2006.72","DOIUrl":"https://doi.org/10.1109/ISQED.2006.72","url":null,"abstract":"Gate-length biasing is a runtime leakage reduction technique that leverages on the short-channel effect by marginally increasing the gate-length of MOS devices to significantly reduce their leakage current for a small delay penalty. The technique was shown to work effectively with multi-threshold-voltage assignment, the only mainstream approach for runtime leakage reduction. Typically, designers use threshold voltages selected by the foundries to optimize their designs. Higher threshold-voltage devices, that are less leaky but slow, are assigned to non-critical paths and lower threshold-voltage devices, that are fast but leaky, are assigned to critical paths. In this paper we study the effect of modifying threshold voltages set by the foundry on leakage reduction achieved on three large, real-world designs. We assess the impact of the availability of gate-length biasing on threshold voltage selection. We achieve comparable leakage reductions when foundry-set dual threshold voltages are used with biasing than when foundry-set triple threshold voltages are used without biasing. Our results indicate that leakage reductions can be improved if threshold voltages are carefully chosen considering the availability of gate-length biasing. We also observe that foundry-set threshold voltages are not optimal for achieving best possible leakage reductions","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126071335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Process window and device variations evaluation using array-based characterization circuits 使用基于阵列的表征电路的工艺窗口和器件变化评估

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.107

C. Tabery, M. Craig, G. Burbach, B. Wagner, S. McGowan, P. Etter, S. Roling, C. Haidinyak, E. Ehrichs

引用次数: 14

Accurate thermal analysis considering nonlinear thermal conductivity 考虑非线性导热系数的精确热分析

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.20

Anand Ramalingam, D. Pan, Frank Liu, S. Nassif

引用次数: 4

Modular service-oriented platform architecture - a key enabler to SoC design quality 模块化面向服务的平台架构——SoC设计质量的关键推动者

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.89

R. Suoranta

引用次数: 2

Statistical analysis of capacitance coupling effects on delay and noise 电容耦合对时延和噪声影响的统计分析

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.121

U. Narasimha, Binu Abraham, N. Nagaraj

引用次数: 11