{"title":"在完全盐化的130纳米CMOS技术中提高ESD稳健性的假门结构,而无需使用额外的盐化阻挡掩模","authors":"Hsin-Chyh Hsu, M. Ker","doi":"10.1109/ISQED.2006.54","DOIUrl":null,"url":null,"abstract":"NMOS with dummy-gate structure is proposed to significantly improve electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, ESD current is discharged far away from the salicided surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level. The HBM (MM) ESD robustness of the NMOS with dummy-gate structure (W/L = 480 mum/0.18 mum) has been successfully improved from 0.5 kV (125 V) to 1.5 kV (325 V) in a 130-nm fully-salicided CMOS process. Under the same layout area of the gate-grounded NMOS (ggNMOS), HBM (MM) ESD level can be improved over 300% (260%) by the proposed dummy-gate structure. The proposed dummy-gate structure is fully processed compatible to general salicided CMOS processes without additional mask, which is very cost-efficient for application in the IC products","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask\",\"authors\":\"Hsin-Chyh Hsu, M. Ker\",\"doi\":\"10.1109/ISQED.2006.54\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"NMOS with dummy-gate structure is proposed to significantly improve electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, ESD current is discharged far away from the salicided surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level. The HBM (MM) ESD robustness of the NMOS with dummy-gate structure (W/L = 480 mum/0.18 mum) has been successfully improved from 0.5 kV (125 V) to 1.5 kV (325 V) in a 130-nm fully-salicided CMOS process. Under the same layout area of the gate-grounded NMOS (ggNMOS), HBM (MM) ESD level can be improved over 300% (260%) by the proposed dummy-gate structure. The proposed dummy-gate structure is fully processed compatible to general salicided CMOS processes without additional mask, which is very cost-efficient for application in the IC products\",\"PeriodicalId\":138839,\"journal\":{\"name\":\"7th International Symposium on Quality Electronic Design (ISQED'06)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-03-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"7th International Symposium on Quality Electronic Design (ISQED'06)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2006.54\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"7th International Symposium on Quality Electronic Design (ISQED'06)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2006.54","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask
NMOS with dummy-gate structure is proposed to significantly improve electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, ESD current is discharged far away from the salicided surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level. The HBM (MM) ESD robustness of the NMOS with dummy-gate structure (W/L = 480 mum/0.18 mum) has been successfully improved from 0.5 kV (125 V) to 1.5 kV (325 V) in a 130-nm fully-salicided CMOS process. Under the same layout area of the gate-grounded NMOS (ggNMOS), HBM (MM) ESD level can be improved over 300% (260%) by the proposed dummy-gate structure. The proposed dummy-gate structure is fully processed compatible to general salicided CMOS processes without additional mask, which is very cost-efficient for application in the IC products