在完全盐化的130纳米CMOS技术中提高ESD稳健性的假门结构,而无需使用额外的盐化阻挡掩模

Hsin-Chyh Hsu, M. Ker
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引用次数: 2

摘要

在全盐化CMOS技术中,采用假栅结构的NMOS可以显著提高静电放电(ESD)的鲁棒性。通过使用这种结构,放电的ESD电流远离NMOS的盐化表面通道,因此NMOS可以维持更高的ESD水平。在130纳米全盐化CMOS工艺中,具有假栅结构(W/L = 480 /0.18)的NMOS的HBM (MM) ESD稳健性从0.5 kV (125 V)成功提高到1.5 kV (325 V)。在相同栅极接地NMOS (ggNMOS)布局面积的情况下,提出的假栅结构可将HBM (MM) ESD电平提高300%(260%)以上。所提出的假门结构与一般的盐化CMOS工艺完全兼容,无需额外的掩模,在IC产品中的应用具有很高的成本效益
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask
NMOS with dummy-gate structure is proposed to significantly improve electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, ESD current is discharged far away from the salicided surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level. The HBM (MM) ESD robustness of the NMOS with dummy-gate structure (W/L = 480 mum/0.18 mum) has been successfully improved from 0.5 kV (125 V) to 1.5 kV (325 V) in a 130-nm fully-salicided CMOS process. Under the same layout area of the gate-grounded NMOS (ggNMOS), HBM (MM) ESD level can be improved over 300% (260%) by the proposed dummy-gate structure. The proposed dummy-gate structure is fully processed compatible to general salicided CMOS processes without additional mask, which is very cost-efficient for application in the IC products
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