7th International Symposium on Quality Electronic Design (ISQED'06)最新文献_第10页

Constant impedance scaling paradigm for scaling LC transmission lines LC传输线的恒阻抗缩放范例

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.38

J. Balachandran, S. Brebels, G. Carchon, W. Raedt, E. Beyne, M. Kuijk, B. Nauwelaers

引用次数: 3

Minimizing ohmic loss in future processor IR events 最小化未来处理器IR事件中的欧姆损耗

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.88

M. Budnik, K. Roy

引用次数: 0

Efficient model update for general link-insertion networks 一般链路插入网络的有效模型更新

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.55

Zhuo Feng, Peng Li, Jiang Hu

{"title":"Efficient model update for general link-insertion networks","authors":"Zhuo Feng, Peng Li, Jiang Hu","doi":"10.1109/ISQED.2006.55","DOIUrl":"https://doi.org/10.1109/ISQED.2006.55","url":null,"abstract":"Link insertion has been proposed as a means of incremental design to improve performance robustness of linear passive networks. In clock network design, links can be inserted between subnetworks to reduce the variability of clock skews introduced by process and environmental fluctuations, thereby improving the network's immunity to PVT variations. Under these scenarios, it is desired to incrementally compute a reduced-order model for the updated network in order to efficiently evaluate the effectiveness of link insertions. In this paper, we present an efficient model update scheme for general link-insertion networks. By updating the Krylov projection subspace used in model order reduction, the proposed scheme can efficiently compute a reduced-order model for the network with inserted links. More generally, we extend the proposed approach to consider the merging of a (small) multiple-input linear network with a much larger network. We demonstrate the usage of the proposed technique for clock networks and general RLC circuits with an arbitrary number of link insertions as well as the more general case where the inserted links are in the form of a linear network","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130373131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Sensing margin analysis of MLC flash memories using a novel unified statistical model 基于统一统计模型的MLC闪存感知裕度分析

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.113

Young-Gu Kim, Sang-Hoon Lee, Dae-Han Kim, Jae-Woo Im, Sung-Eun Yu, Dae-Wook Kim, Young-Kwan Park, J. Kong

引用次数: 3

A formal verification method of scheduling in high-level synthesis 高级综合中调度的形式化验证方法

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.10

C. Karfa, C. Mandal, D. Sarkar, S. Pentakota, C. Reade

引用次数: 42

Interconnect and thermal-aware floorplanning for 3D microprocessors 三维微处理器的互连和热感知布局

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.77

W. Hung, G. Link, Yuan Xie, N. Vijaykrishnan, M. J. Irwin

引用次数: 192

Future Memory Technology Trends and Challenges 未来内存技术的趋势和挑战

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.69

Changhyun Kim

{"title":"Future Memory Technology Trends and Challenges","authors":"Changhyun Kim","doi":"10.1109/ISQED.2006.69","DOIUrl":"https://doi.org/10.1109/ISQED.2006.69","url":null,"abstract":"As memory market enters the Gigabit and GHz range with consumers demanding ever higher performance and diversified applications, new types of devices are being developed in order to keep up with the scaling requirements for cost reduction. Among these devices are well-known ones such as the recessed channel transistors, but also FinFET and vertically stacked transistors for DRAM and charge trap devices for Flash memory. The latter ones are still not at a manufacturable stage yet. Even more exotic memories implement new materials and stacked architectures on the cell, chip and package level. On the performance side, increasing speeds require higher time resolutions. The future difficulties of process control by far exceed those of conventional planar devices. Therefore device characteristics are expected to show ever increasing PVT variations. As these variations become more and more inevitable, especially as dimensions approach the atomic scale, negative effects on circuit and device performances have to be prevented by new, appropriate methods of 3D device modeling and circuit design which consider the mentioned parameter variations. In this talk such challenges will be discussed as well as some approaches to overcome them. An outlook will also be given about the memory technology trends in the next decades.","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123399907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Constructing current-based gate models based on existing timing library 基于现有时序库构建基于电流的栅极模型

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.39

A. Kahng, Bao Liu, Xu Xu

{"title":"Constructing current-based gate models based on existing timing library","authors":"A. Kahng, Bao Liu, Xu Xu","doi":"10.1109/ISQED.2006.39","DOIUrl":"https://doi.org/10.1109/ISQED.2006.39","url":null,"abstract":"Current-based gate modeling achieves a new level of accuracy in nanoscale design timing and signal integrity analysis. However, to generate current-based gate models requires additional pre-characterization of the gate, e.g., in the form of a new or an extended timing library format. We construct current-based gate models based on the existing Liberty timing library format without further pre-characterization. We present an inverse problem formulation, and propose to solve the problem by quadratic polynomial regression. Our constructed current-based gate models find applications in timing, power, and signal integrity verifications for improved accuracy in library-compatible flows, e.g., to include power supply voltage drop effect in gate delay calculation without further pre-characterization, to calculate gate supply current, etc. Our experimental results show our constructed current-based gate models achieve slightly less accurate results, e.g., within 4.6%(8.6%), than pre-characterized current-based gate models, e.g., within 4.3%(4.4%), of SPICE results in gate delay calculation for ideal (degraded) power supply voltage, and accurate gate supply current calculation","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122814368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Formal verification of pipelined microprocessors with delayed branches 具有延迟分支的流水线微处理器的形式化验证

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.68

M. Velev

引用次数: 3

Transaction level error susceptibility model for bus based SoC architectures 基于总线的SoC体系结构的事务级错误敏感性模型

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.138

Ing-Chao Lin, S. Srinivasan, N. Vijaykrishnan, N. Dhanwada

引用次数: 10