7th International Symposium on Quality Electronic Design (ISQED'06)最新文献_第5页

Impact of NBTI on SRAM read stability and design for reliability NBTI对SRAM读取稳定性和可靠性设计的影响

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.73

Sanjay V. Kumar, C. Kim, S. Sapatnekar

引用次数: 345

Gate sizing and replication to minimize the effects of virtual ground parasitic resistances in MTCMOS designs 栅极尺寸和复制，以尽量减少MTCMOS设计中虚拟地寄生电阻的影响

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.70

Chanseok Hwang, C. Kang, Massoud Pedram

引用次数: 10

ConvexSmooth: a simultaneous convex fitting and smoothing algorithm for convex optimization problems conexsmooth:一个同时用于凸优化问题的凸拟合和平滑算法

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.40

Sanghamitra Roy, C. C. Chen

{"title":"ConvexSmooth: a simultaneous convex fitting and smoothing algorithm for convex optimization problems","authors":"Sanghamitra Roy, C. C. Chen","doi":"10.1109/ISQED.2006.40","DOIUrl":"https://doi.org/10.1109/ISQED.2006.40","url":null,"abstract":"Convex optimization problems are very popular in the VLSI design society due to their guaranteed convergence to a global optimal point. Table data is often fitted into analytical forms like posynomials to make them convex. However, fitting the look-up tables into posynomial forms with minimum error itself may not be a convex optimization problem and hence excessive fitting errors may be introduced. In recent literature numerically convex tables have been proposed. These tables are created optimally by minimizing the perturbation of data to make them numerically convex. But since these tables are numerical, it is extremely important to make the table data smooth, and yet preserve its convexity. Smoothness will ensure that the convex optimizer behaves in a predictable way and converges quickly to the global optimal point. In this paper, we propose to simultaneously create optimal numerically convex look-up tables and guarantee smoothness in the data. We show that numerically \"convexifying\" and \"smoothing\" the table data with minimum perturbation can be formulated as a convex semidefinite optimization problem and hence optimality can be reached in polynomial time. We present our convexifying and smoothing results on industrial cell libraries. ConvexSmooth shows 14times reduction in fitting error over a well-developed posynomial fitting algorithm","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126802661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Adding Manufacturability to the Quality of Results 将可制造性添加到结果质量中

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.21

R. Camposano

{"title":"Adding Manufacturability to the Quality of Results","authors":"R. Camposano","doi":"10.1109/ISQED.2006.21","DOIUrl":"https://doi.org/10.1109/ISQED.2006.21","url":null,"abstract":"Traditionally, IC designers have been able to define \"Quality of Results\" (QoR) primarily in terms of functionality, area, speed, and power. Hardly a backward glance was given to what manufacturers would do once the designs were handed off to them. Today, manufacturability has clearly joining the ranks of QoR. This is particularly true for technology nodes at 65 nanometers (nm) and below. Yield loss mechanisms, both functional and parametric, have become dependant on the design and increasingly, as geometries continue to shrink to 45nm and below, must be addressed from design to lithography to process. In this talk, we will examine some solutions being used to ensure quality in this area of concern. Topics include incorporating yield-rated cells and probabilistic methods such as statistical timing analysis to address yield losses early in the design. Test is being used for diagnosis. Routing optimization techniques such as minimizing critical areas for shorts and open circuits, wire-spreading, redundant vias and dummy metal fills improve manufacturability for metal layers. Further down the tool chain, resolution enhancement techniques (RET) used in mask synthesis addresses lithography, improving printability and hence yield. Manufacturing process knowledge is becoming increasingly important in design to enable effective yield modeling. TCAD models are making their way into manufacturing, helping, for example, to simulate statistical variations of electrical parameters as a function of process parameters.","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134100725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Transistor-level optimization of supergates 超级栅极的晶体管级优化

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.139

D. Kagaris, T. Haniotakis

引用次数: 8

Tutorial 1: Emerging Technologies for VLSI Design 教程1:VLSI设计的新兴技术

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.140

R. Joshi, K. Banerjee, A. DeHon

引用次数: 0

Improving transient error tolerance of digital VLSI circuits using robustness compiler (ROCO) 利用鲁棒性编译器(ROCO)提高数字VLSI电路的暂态容错性

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.75

Chong Zhao, S. Dey

引用次数: 25

Device and Technology Challenges for Nanoscale CMOS 纳米级CMOS的器件和技术挑战

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.49

H. Wong

{"title":"Device and Technology Challenges for Nanoscale CMOS","authors":"H. Wong","doi":"10.1109/ISQED.2006.49","DOIUrl":"https://doi.org/10.1109/ISQED.2006.49","url":null,"abstract":"With the introduction of 90 nm node technology, silicon CMOS is already at the nanoscale. There is no doubt that the semiconductor industry desires to stay on the historical rate of cost/performance/density improvement as exemplified by the International Technology Roadmap for Semiconductors (ITRS). The challenges for continued device scaling are daunting. At the highest level, the challenges are: (1) delivering cost/performance improvement while at the same time containing power consumption/dissipation, (2) control of device variations, and (3) device/circuit/system co-design and integration. New devices and new materials offer new opportunities for solving the challenges of continued improvement. In this talk, we give an overview of the device options being considered for CMOS logic technologies from 45 nm to 22 nm and beyond. Technology options include the use of device structures (multi-gate FET) and transport-enhanced channel materials (strained Si, Ge). Beyond the 22 nm node, research are underway to explore even more adventurous options such as III-V compound semiconductors as channel materials, metal Schottky source/drain. Beyond that time horizon, there is the question of whether new materials and fabrication methods such as carbon nanotubes, semiconductor nanowires and self-assembly techniques will make an impact in nanoscale CMOS technologies. We survey the state-of-the-art of these emerging devices and technologies and discuss the research opportunities going forward. We conclude with a discussion of the interaction between device design and the circuit/system architecture and how this interaction will change the landscape of technology development in the future.","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116743679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Stress-aware design methodology 应力感知设计方法

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.124

V. Moroz, Lee Smith, Xi-Wei Lin, D. Pramanik, G. Rollins

引用次数: 44

Monte Carlo-alternative probabilistic simulations for analog systems 模拟系统的蒙特卡罗替代概率模拟

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.90

R. Topaloglu

引用次数: 5