Transistor-level optimization of supergates

Abstract

The chip area and delay in digital VLSI design depends on the number of transistors that are used for the logic gates involved. While the determination of a series-parallel implementation can be straightforward once a simplified expression of the function is available, this may not be an optimum solution. In the current paper an improved approach for determining a satisfactory solution for complex gates is presented. Experimental results demonstrate the efficiency of the approach