Gate sizing and replication to minimize the effects of virtual ground parasitic resistances in MTCMOS designs

Abstract

The Multi-Threshold CMOS (MTCMOS) technique can significantly reduce sub-threshold leakage currents during the circuit sleep (standby) mode by adding high-Vth power switches (sleep transistors) to low-Vth logic cells. During the active mode of the circuit, the high-Vth transistors and the virtual ground network can be modeled as resistors, which in turn cause voltage of the virtual ground node to rise thereby degrading the switching speed of the logic cells. This paper introduces a new design methodology that minimizes the impact of virtual ground parasitic resistances on the performance of an MTCMOS circuit by using gate resizing and logic restructuring (i.e., gate replication.) Experimental results show that the proposed techniques are highly effective in making the MTCMOS circuits robust with respect to such parasitic resistance effects