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Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines最新文献

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Virtual hardware for graphics applications using FPGAs 使用fpga的图形应用的虚拟硬件
Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines Pub Date : 1994-04-10 DOI: 10.1109/FPGA.1994.315598
S. Singh, P. Bellec
{"title":"Virtual hardware for graphics applications using FPGAs","authors":"S. Singh, P. Bellec","doi":"10.1109/FPGA.1994.315598","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315598","url":null,"abstract":"The suitability of FPGA devices for implementing graphics algorithms is analysed by a series of experiments. The performance of simple and complicated graphics algorithms on two kinds of FPGAs are compared with the performance of existing custom graphics chips and against general-purpose processors with specialised instruction sets. Various architectures for incorporating FPGA-based systems into graphics workstations are discussed. Finally, a new design method (based on virtual memory) is presented that exploits the dynamically reconfigurable nature of FPGAs.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116663717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
A field programmable multi-chip module (FPMCM) 现场可编程多芯片模块(FPMCM)
Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines Pub Date : 1994-04-10 DOI: 10.1109/FPGA.1994.315592
J. Darnauer, P. Garay, Tsuyoshi Isshiki, J. Ramirez, Wayne Wei-Ming DaiComputer
{"title":"A field programmable multi-chip module (FPMCM)","authors":"J. Darnauer, P. Garay, Tsuyoshi Isshiki, J. Ramirez, Wayne Wei-Ming DaiComputer","doi":"10.1109/FPGA.1994.315592","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315592","url":null,"abstract":"Multi-chip module (MCM) packaging can reduce the cost and increase the utility of field programmable systems. We are currently developing a first generation field programmable multi-chip module (FPMCM) as a test vehicle for a particular MCM technology. We present the advantages of MCM for field programmable systems and develop analytical models for estimating the capacity of FPMCM architectures based on Rent's rule. These models are used to generate the architecture of our first generation prototype which employs smaller FPGA die and a mixture of direct and switched interconnect. We conclude with a discussion of the challenges and opportunities that FPMCMs face.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131458390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A reconfigurable Monte-Carlo clustering processor (MCCP) 可重构蒙特卡罗聚类处理器(MCCP)
Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines Pub Date : 1994-04-10 DOI: 10.1109/FPGA.1994.315600
C. Cowen, S. Monaghan
{"title":"A reconfigurable Monte-Carlo clustering processor (MCCP)","authors":"C. Cowen, S. Monaghan","doi":"10.1109/FPGA.1994.315600","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315600","url":null,"abstract":"A generic Monte Carlo problem architecture, implemented earlier in a dedicated FPGA computer (Monaghan, O'Brien and Noakes, 1991; Monaghan, 1993; Monaghan and Cowen, 1993), is extended to incorporate a wider range of more complex Monte Carlo and percolation problems. The new algorithms, which are implemented in the same computer architecture, execute an order of magnitude faster than on comparable DSP hardware, as with the earlier and simpler algorithms.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133875356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
FPGA-based stochastic neural networks-implementation 基于fpga的随机神经网络实现
Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines Pub Date : 1994-04-10 DOI: 10.1109/FPGA.1994.315612
S.L. Bade, B. L. Hutchings
{"title":"FPGA-based stochastic neural networks-implementation","authors":"S.L. Bade, B. L. Hutchings","doi":"10.1109/FPGA.1994.315612","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315612","url":null,"abstract":"Reconfigurable field-programmable gate arrays (FPGAs) provide an effective programmable resource for implementing hardware-based artificial neural networks (ANNs). They are low cost, readily available and reconfigurable-all important advantages for ANN applications. However, FPGAs lack the circuit density necessary to implement large parallel ANNs with many thousands of synapses. This paper presents an architecture that makes it feasible to implement large ANNs with FPGAs. The architecture combines stochastic computation techniques with a novel lookup-table-based architecture that fully exploits the lookup-table structure of many FPGAs. This lookup-table-based architecture is extremely efficient: it is capable of supporting up to two synapses per configurable logic block (CLB). In addition, the architecture is simple to implement, self-contained (weights are stored directly in the synapse), and scales easily across multiple chips.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123853216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 121
The Nano Processor: a low resource reconfigurable processor 纳米处理器:一种低资源可重构处理器
Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines Pub Date : 1994-04-10 DOI: 10.1109/FPGA.1994.315595
M. Wirthlin, B. Hutchings, K. Gilson
{"title":"The Nano Processor: a low resource reconfigurable processor","authors":"M. Wirthlin, B. Hutchings, K. Gilson","doi":"10.1109/FPGA.1994.315595","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315595","url":null,"abstract":"Reconfigurable logic systems approach the performance of application-specific integrated circuits (ASICs) while retaining much of the generality of conventional computing systems through reconfiguration. Unfortunately, the development of these systems, unlike conventional software systems, is hardware-intensive, requiring significant hardware development time. One way to introduce a more flexible development approach is to implement a customizable stored-program processor. For a given application, the designer can develop customized hardware to increase performance and then control the sequencing and operation of this hardware with software. Development time can be significantly reduced because conventional software development tools, e.g. assemblers and compilers, can be used to quickly develop new applications on the customized processor. This paper presents the Nano Processor, a fully customizable reconfigurable processor, together with its integrated assembler, that has been successfully implemented on the Xilinx 3000 series field programmable gate array (FPGA).<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"100 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120884778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 79
Pin assignment for multi-FPGA systems 多fpga系统的引脚分配
Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines Pub Date : 1994-04-10 DOI: 10.1109/FPGA.1994.315593
S. Hauck, G. Borriello
{"title":"Pin assignment for multi-FPGA systems","authors":"S. Hauck, G. Borriello","doi":"10.1109/FPGA.1994.315593","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315593","url":null,"abstract":"There is currently great interest in using systems of FPGAs for logic emulators, custom computing devices, and software accelerators. An important step in making these technologies more generally useful is to develop completely automatic mapping tools from high-level specifications to FPGA programming files. We examine one step in this automatic mapping process, the selection of FPGA pins to use for routing inter-FPGA signals. We present an algorithm that greatly increases mapping speed while also improving mapping quality.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125691041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
PAM programming environments: practice and experience PAM编程环境:实践与经验
Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines Pub Date : 1994-04-10 DOI: 10.1109/FPGA.1994.315599
Patrice Bertin, Herv
{"title":"PAM programming environments: practice and experience","authors":"Patrice Bertin, Herv","doi":"10.1109/FPGA.1994.315599","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315599","url":null,"abstract":"Digital Equipment's Paris Research Laboratory started to investigate the use of FPGA-based reconfigurable hardware accelerators in 1988. We call them PAMs for Programmable Active Memories. Over the past six years, we have designed and implemented four generations of PAM hardware and four generations of PAM programming environments. Several dozen people, ranging from inexperienced students to senior hardware designers, have used our systems. A wide range of applications belonging to several important application domains have demonstrated the interest of these novel computing devices. In this paper we present the software lessons we draw from this collective experience.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114379063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 76
Hardware-software codesign of multidimensional programs 多维程序的软硬件协同设计
Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines Pub Date : 1994-04-10 DOI: 10.1109/FPGA.1994.315604
Wayne Luk, Teddy Wu, Ian Page
{"title":"Hardware-software codesign of multidimensional programs","authors":"Wayne Luk, Teddy Wu, Ian Page","doi":"10.1109/FPGA.1994.315604","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315604","url":null,"abstract":"Presents a method for parametrised partitioning of multidimensional programs for acceleration using a hardware coprocessor. The method involves a divide-and-conquer structure, with the \"divide\" and \"merge\" phases carried out by a general-purpose processor, while the \"conquer\" phase is handled by application-specific hardware. The partitioning strategy has been captured in a simple functional language, and we have automated the production of partitioned programs in this language. Our approach has been tested on an FPGA-based system using a number of computer vision algorithms, including the Canny edge detector, and the performance is compared against executing the programs on the PC host.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128204450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Compiling to the gate level for a reconfigurable co-processor 编译到可重构协处理器的门级
Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines Pub Date : 1994-04-10 DOI: 10.1109/FPGA.1994.315607
WO David, Kevin Forward
{"title":"Compiling to the gate level for a reconfigurable co-processor","authors":"WO David, Kevin Forward","doi":"10.1109/FPGA.1994.315607","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315607","url":null,"abstract":"This paper describes a programmable coprocessor. A C-compiler has been written which compiles C code to the gate level relieving the programmer of the onerous task of programming the coprocessor. As not all of the code in most C programs will fit into the coprocessors FPGA, programs are first compiled using a standard C compiler. These programs are then profiled to determine which parts of the code make the most intense use of the processor. These parts are then compiled to the gate level and implemented in the coprocessor. Speedups in program execution time of about 20 are obtained by this method by comparison with an IPC Sparcstation.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134196741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Behavioral synthesis for FPGA-based computing 基于fpga计算的行为综合
Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines Pub Date : 1994-04-10 DOI: 10.1109/FPGA.1994.315591
H. Schmit, Lawrence Amstein, D. Thomas, E. Lagnese
{"title":"Behavioral synthesis for FPGA-based computing","authors":"H. Schmit, Lawrence Amstein, D. Thomas, E. Lagnese","doi":"10.1109/FPGA.1994.315591","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315591","url":null,"abstract":"We describe how a behavioral synthesis system can be used to create designs for FPGA-based computing systems directly from a specification of the desired algorithm. This higher level of specification reduces design times and design errors. Our target hardware is called the Rasa Board and is composed of three Xilinx FPGAs interconnected with Aptix Field Programmable Interconnect Chips. We address two significant challenges in this research effort: the synthesis of multiple FPGA designs, and the improvement of the design through designer interaction.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129579249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
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