Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines最新文献_第3页

Finding lines and building pyramids with SPLASH 2 寻找线和建筑金字塔与飞溅2

Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines Pub Date : 1994-04-10 DOI: 10.1109/FPGA.1994.315608

Lynn Abbott, Peter M. Athanas, Luna Chen, Robert L. Elliott

引用次数: 64

Comparing the performance of FPGA-based custom computers with general-purpose computers for DSP applications 比较基于fpga的定制计算机与DSP应用的通用计算机的性能

Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines Pub Date : 1994-04-10 DOI: 10.1109/FPGA.1994.315609

Neil W. Bergmann, J. C. Mudge

引用次数: 29

Field programmable gate array based reconfigurable preprocessor 基于现场可编程门阵列的可重构预处理器

Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines Pub Date : 1994-04-10 DOI: 10.1109/FPGA.1994.315597

B. Box

{"title":"Field programmable gate array based reconfigurable preprocessor","authors":"B. Box","doi":"10.1109/FPGA.1994.315597","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315597","url":null,"abstract":"Custom hardware implementations of preprocessors are seldom reusable, flexible enough to allow algorithm exploration or quickly realized. The Configurable Hardware Algorithm Mappable Preprocessor (CHAMP) technology is a solution to these problems. Recent developments in FPGA hardware and software have made a reconfigurable preprocessor with custom hardware performance but generic hardware flexibility possible. The key advancements are larger, faster RAM and electrically erasable devices, routers with deadline timers, and synthesis tools which can work with user-definable macros. Ongoing work in the areas of partitioning, synthesis, placement, packaging and compilation will make reconfigurable preprocessors more powerful. The present CHAMP implementation is based on Xilinx FPGAs. Its architecture consists of multiple reconfigurable processing elements connected through both a ring network and a global crossbar network. It is packaged as a VME 6U/spl times/160 slave board with two high-speed reconfigurable parallel interfaces. In order to allow development at the algorithm level while retaining preprocessor performance, off-the-shelf development tools have been integrated with a custom library of macros as part of the CHAMP design process. As a verification of the CHAMP technology, an advanced IR missile warning application was mapped onto the CHAMP architecture achieving greater than 1 billion operations/sec of real-time throughput while utilizing 75% of the CHAMP board's processing resources.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122433031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs 一种利用fpga在自适应架构上高效执行程序的异步方法

Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines Pub Date : 1994-04-10 DOI: 10.1109/FPGA.1994.315606

L. Agarwal, M. Wazlowski, S. Ghosh

引用次数: 44