Georges Quénot, I. Kraljic, Jocelyn Serot, Bertrand Zavidovique
{"title":"A reconfigurable compute engine for real-time vision automata prototyping","authors":"Georges Quénot, I. Kraljic, Jocelyn Serot, Bertrand Zavidovique","doi":"10.1109/FPGA.1994.315605","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315605","url":null,"abstract":"Describes a reconfigurable computer engine called the Data-Flow Functional Computer (DFFC), which is dedicated to rapid prototyping of real-time vision automata. The computer consists of a regular 3D array of very coarse grain application-specific FPGAs, called the 'field-programmable operator array' (FPOA). Each FPOA includes two configurable data paths and ten input/output ports. Specific development tools allow easy and efficient use of the computer. A high-level description (in a functional language) is compiled into a DFFC configuration using an operator library. Several significant applications (connected component labelling, nonlinear filtering, coloured object tracking) have been implemented using our tools. An environment for automatic derivation of vision automata from a DFFC configuration is currently under development.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127163185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"DPGA-coupled microprocessors: commodity ICs for the early 21st Century","authors":"A. DeHon","doi":"10.1109/FPGA.1994.315596","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315596","url":null,"abstract":"During the past decade, the microprocessor has become a key commodity component for building all kinds of computational systems. During this time frame, large reconfigurable logic arrays have exploited the same advances in IC fabrication technology to emerge as viable system building blocks. Looking at both the technology prospects and application requirements, there is compelling evidence that microprocessors with integrated reconfigurable logic arrays will be a primary building block for future computing systems. In this paper, we look at the role such components can play in building high-performance and economical systems, as well as the ripe technological outlook. We note how the tight integration of reconfigurable logic into the processor can overcome some of the major limitations of contemporary attached reconfigurable computer engines. We specifically consider the use of integrated dynamically programmable gate array (DPGA) structures for the configurable logic, and examine the advantages that rapid reconfiguration provides in this application.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129252564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Dahl, J. Babb, Russell Tessier, S. Hanono, D. Hoki, Anant Agarwal
{"title":"Emulation of the Sparcle microprocessor with the MIT Virtual Wires emulation system","authors":"M. Dahl, J. Babb, Russell Tessier, S. Hanono, D. Hoki, Anant Agarwal","doi":"10.1109/FPGA.1994.315594","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315594","url":null,"abstract":"Describes a complete FPGA-based emulation software system using Virtual Wires technology and present the results of emulating an 18K-gate ASIC implementation of a modified Sparc microprocessor. Virtual Wires overcomes the pin-count limitation that formerly restricted the efficiency of FPGA-based logic emulators. The MIT Virtual Wires softwire compiler accepts a netlist description of the system to be emulated and produces programming information for the FPGA hardware, an inexpensive ($3000) board designed for Virtual Wires in-circuit emulation. The compiler also provides an interface to standard logic simulator tools for hardware accelerated simulation. We discuss innovative features of the compiler system and knowledge gained during its construction. A comparison is made of different implementations of the on-chip Virtual Wires circuitry synthesized by the compiler. Several enhancements to the original Virtual Wires concept are presented that improve the emulation speed and FPGA utilization.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131082923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Global control synthesis for an MIMD/FPGA machine","authors":"P. Dhaussy, J. Filloque, B. Pottier, S. Rubini","doi":"10.1109/FPGA.1994.315603","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315603","url":null,"abstract":"Embedding a FPGA circular array into MIMD architectures allows one to synthesize fine-grain circuits for global computation support. These circuits operate concurrently with the distributed applications. They provide specific speed-up or additional services, such as communication protocols or global controllers. This article describes an architectural model for such controllers with practical examples implemented on the ArMen FPGA-multiprocessor. A multi-assignment language derived from the UNITY formalism is proposed, to implement the controllers with a high degree of parallelism. Their hardware synthesis principles are given.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124208534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"CAFCA (Compact Accelerator For Cellular Automata): the metamorphosable machine","authors":"P. Marchal, E. Sanchez","doi":"10.1109/FPGA.1994.315601","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315601","url":null,"abstract":"Partial differential equations have conventionally formed a basis for mathematical models of continuous systems. Cellular automata provide an alternative approach. The large scope of applications of cellular automata (in biology, physics, operational research, sociology, computer science and so on) will surely increase the need of such a tool. The basic constitutive cells are discrete and ideally suited to simulation by digital computers. Their property of only interacting in a local environment naturally leads to a new idea of processing: cellular processing. In fact, the simulation of cellular automata with mainframe computers, even with parallel multiprocessors, is always slowed down by the input/output bottleneck. This paper describes the architecture of a compact accelerator for cellular automata. This multi-expandable machine is based on a pipeline architecture which concurrently performs computations and displays results. The underlying principle is to spy on the display bus by grabbing the data flow pouring out to the display device and simultaneously to evaluate the state of each automaton in the network. The performance of the machine reaches the video rate: it computes and displays the state of the 1024/spl times/1024 16-bit automata 24 times per second. FPGAs play a key role in the architecture of the system.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124420011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An FPGA-based custom coprocessor for automatic image segmentation applications","authors":"G.J. Gent, S.R. Smith, R.L. Haviland","doi":"10.1109/FPGA.1994.315610","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315610","url":null,"abstract":"We describe a customized computing platform we are developing to accelerate a computer vision application. An FPGA-based coprocessor solution is derived which accelerates most of the compute-intensive calculations of a template deforming image segmentation algorithm. Design issues are identified and performance results reported. The results are parameterized so that alternative solutions can be evaluated according to technological advances. We discuss how implementing such a design with available reconfigurable logic platforms can be a worthwhile tool for the development of customized FPGA-based computing solutions.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126112662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A reconfigurable data-driven ALU for Xputers","authors":"R. Hartenstein, R. Kress, H. Reinig","doi":"10.1109/FPGA.1994.315602","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315602","url":null,"abstract":"A reconfigurable data-driven datapath architecture for ALUs is presented which may be used for custom computing machines (CCMs), Xputers (a class of CCMs) and other adaptable computer systems as well as for rapid prototyping of high speed datapaths. Fine grained parallelism is achieved by using simple reconfigurable processing elements which are called datapath units (DPUs). The word-oriented datapath simplifies the mapping of applications onto the architecture. Pipelining is supported by the architecture. The programming environment allows automatic mapping of the operators from high level descriptions. Two implementations, one by FPGAs and one with standard cells are shown.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130225333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Axel Jantsch, P. Ellervee, Johnny Öberg, A. Hemani
{"title":"A case study on hardware/software partitioning","authors":"Axel Jantsch, P. Ellervee, Johnny Öberg, A. Hemani","doi":"10.1109/FPGA.1994.315586","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315586","url":null,"abstract":"We present an analysis of a fully automatic method to accelerate standard software in C or C++ by use of field programmable gate arrays. Traditional compiler techniques are applied to the hardware/software partitioning problem and a compiler is linked to state of the art hardware synthesis tools. Time critical regions are identified by means of profiling and are automatically implemented in user programmable logic with high level and logic synthesis design tools. The underlying architecture is an add-on board with user programmable logic connected to a Spare based workstation via the system bus. We present an analysis and case study of this method. Eight programs are used as test cases and the data collected by applying this method to programs is used to discuss potentials and limitations of this and similar methods. We discuss architectural parameters, programming language properties, and analysis techniques.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114101838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"From high level programming model to FPGA machines","authors":"J. Banâtre, D. Lavenier, M. Vieillot","doi":"10.1109/FPGA.1994.315590","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315590","url":null,"abstract":"This paper presents an approach for deriving a FPGA machine from a high level parallel programming model. The model is based on the chemical reaction metaphor : the data structure is a multiset and the computation can be seen as a succession of chemical reactions consuming and producing new elements according to specific rules. Von Newman architecture are not suited to this programming style; we show the utility of FPGAs for deriving adapted hardware architectures. Feasibility has been demonstrated on the DEC-PRL Perle-1 board with implementation of a representative algorithm.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125021999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Density enhancement of a neural network using FPGAs and run-time reconfiguration","authors":"James G. Eldredge, B. L. Hutchings","doi":"10.1109/FPGA.1994.315611","DOIUrl":"https://doi.org/10.1109/FPGA.1994.315611","url":null,"abstract":"Run-time reconfiguration is a way of more fully exploiting the flexbility of reconfigurable FPGAs. The run-time reconfiguration artificial neural network (RRANN) uses ran-time reconfiguration to increase the hardware density of FPGAs. The RRANN architecture also allows large amounts of parallelism to be used and is very scalable. RRANN divides the back-propagation algorithm into three sequential executed stages and configures the FPGAs to execute only one stage at a time. The FPGAs are reconfigured as part of normal execution in order to change stages. Using reconfigurability in this way increases the number of hardware neurons a single Xilinx XC3090 can implement by 500%. Performance is effected by reconfiguration overhead, but this overhead becomes insignificant in large networks. This overhead is made even more insignificant with improved configuration methods. Run-time reconfiguration is a flexible realization of the time/space trade-off. The RRANN architecture has been designed and built using commercially available hardware, and its performance has been measured.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116416103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}