{"title":"编译到可重构协处理器的门级","authors":"WO David, Kevin Forward","doi":"10.1109/FPGA.1994.315607","DOIUrl":null,"url":null,"abstract":"This paper describes a programmable coprocessor. A C-compiler has been written which compiles C code to the gate level relieving the programmer of the onerous task of programming the coprocessor. As not all of the code in most C programs will fit into the coprocessors FPGA, programs are first compiled using a standard C compiler. These programs are then profiled to determine which parts of the code make the most intense use of the processor. These parts are then compiled to the gate level and implemented in the coprocessor. Speedups in program execution time of about 20 are obtained by this method by comparison with an IPC Sparcstation.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"98 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":"{\"title\":\"Compiling to the gate level for a reconfigurable co-processor\",\"authors\":\"WO David, Kevin Forward\",\"doi\":\"10.1109/FPGA.1994.315607\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a programmable coprocessor. A C-compiler has been written which compiles C code to the gate level relieving the programmer of the onerous task of programming the coprocessor. As not all of the code in most C programs will fit into the coprocessors FPGA, programs are first compiled using a standard C compiler. These programs are then profiled to determine which parts of the code make the most intense use of the processor. These parts are then compiled to the gate level and implemented in the coprocessor. Speedups in program execution time of about 20 are obtained by this method by comparison with an IPC Sparcstation.<<ETX>>\",\"PeriodicalId\":138179,\"journal\":{\"name\":\"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines\",\"volume\":\"98 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-04-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"21\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FPGA.1994.315607\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FPGA.1994.315607","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Compiling to the gate level for a reconfigurable co-processor
This paper describes a programmable coprocessor. A C-compiler has been written which compiles C code to the gate level relieving the programmer of the onerous task of programming the coprocessor. As not all of the code in most C programs will fit into the coprocessors FPGA, programs are first compiled using a standard C compiler. These programs are then profiled to determine which parts of the code make the most intense use of the processor. These parts are then compiled to the gate level and implemented in the coprocessor. Speedups in program execution time of about 20 are obtained by this method by comparison with an IPC Sparcstation.<>
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