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2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)最新文献

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Design and implementation of 15-4 compressor using 1-bit Semi Domino full adder at 28nm technology 采用1位Semi - Domino全加法器的28纳米技术设计和实现15-4压缩器
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450464
G. Raju, S. Aruna, G. Kumar, S. Krishna
{"title":"Design and implementation of 15-4 compressor using 1-bit Semi Domino full adder at 28nm technology","authors":"G. Raju, S. Aruna, G. Kumar, S. Krishna","doi":"10.1109/PRIMEASIA.2015.7450464","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450464","url":null,"abstract":"In this paper, a 15-4 Compressor for Low power arithmetic operations is presented. A new Low power full adder and 5-3 compressor are used in this 15-4 compressor. Full Adder and 5-3 compressors are realized by Semi Domino logic which is faster and consumes less power than other conventional logics. Objective of this work is to study the power, delay, power delay product of full adders in different logic styles and to study the power, delay, and power delay product of Semi Domino 5-3 compressor architecture with other architectures. Simulation results demonstrate the superiority of the proposed adder circuit against the previous adder circuits in terms of power, delay, PDP. The proposed style gets its benefit in terms of power, delay, PDP. The performance of the adder circuits and compressors is based on TSMC 28nm CMOS process models at the supply voltage of 1V evaluated by comparing of the simulation results obtained from Cadence spectre.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"298 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114852939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Noise figure analysis of 2.5 GHz folded cascode LNA using high-Q layout optimized inductors 采用高q布局优化电感的2.5 GHz折叠级联LNA噪声系数分析
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450477
Shashank Tiwari, V. Vanukuru, J. Mukherjee
{"title":"Noise figure analysis of 2.5 GHz folded cascode LNA using high-Q layout optimized inductors","authors":"Shashank Tiwari, V. Vanukuru, J. Mukherjee","doi":"10.1109/PRIMEASIA.2015.7450477","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450477","url":null,"abstract":"The effect of inductor quality factor (Q) on the noise figure (NF) of a folded cascode low noise amplifier (LNA) is thoroughly studied for different values of DC power consumption. At lower power levels, the contribution of inductor Q towards the overall noise figure is shown to be less. Area optimized inductors with lower Q values can be used in such designs. However, for higher power levels, achievable NF is lower and is significantly affected by the Q of inductors. It is shown that layout optimized high-Q inductors can further reduce the NF by more than 10%. A 2.5 GHz LNA designed and simulated using 0.18 μm RF SOI process is shown to exhibit 1.4 dB NF while consuming 2.5 mW power with the return loss at the input and output better than 30 dB.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129779082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A low hardware complexity time domain quantizer for wideband multibit - ADCs 一种用于宽带多位adc的低硬件复杂度时域量化器
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450479
P. Jha, P. Patra, A. Dutta
{"title":"A low hardware complexity time domain quantizer for wideband multibit - ADCs","authors":"P. Jha, P. Patra, A. Dutta","doi":"10.1109/PRIMEASIA.2015.7450479","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450479","url":null,"abstract":"This paper presents proof of concept of a low hardware complexity time domain quantizer (TDQ) for wideband multibit countinuous time (CT) ΣΔ ADCs. Besides rendering multi-level quantization of the input signal, the proposed scheme generates a two-level loop feedback signal for the modulator. The two-level feedback eliminates the errors emanating from component mismatches in the feedback digital-to-analog converter (DAC) due to process variations. The complete scheme is modeled using Simulink (MATLAB) and is validated through simulation. A 2nd order ΣΔ modulator incorporating the proposed TDQ achieves a dynamic range of 45.7 dB for a bandwidth of 10 MHz and an input sine-wave of -5.78 dBFS amplitude.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133310522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Radiation hardened high resolution timing generator 抗辐射高分辨率定时发生器
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450480
S. Balaji, S. Ramasamy
{"title":"Radiation hardened high resolution timing generator","authors":"S. Balaji, S. Ramasamy","doi":"10.1109/PRIMEASIA.2015.7450480","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450480","url":null,"abstract":"A high resolution timing generator is used as a building block for Time to Digital Converters (TDC) and clock alignment functions. The timing generator is implemented using digital Delay-Locked Loop (DLL). As DLLs are vulnerable to single event effects, the propagation of single-event transients (SETs) single event transients (SETs) is a significant reliability challenge for DLL. The errors signatures following an ion strike in Voltage-Controlled Delay Line (VCDL) can be mitigated using the dual controlled differential delay circuit in combination with sensitive node active charge cancellation (SNACC) for biasing circuit of VCDL. The dual controlled differential delay circuit based VCDL has faster locking with reduced duty cycle error.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115731372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A comparative study of 6T-SRAM cell designed using Symmetrical Double Gate MOSFET and Symmetrical Double Gate Ferroelectric FET 对称双栅MOSFET和对称双栅铁电场效应管设计6T-SRAM电池的比较研究
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450468
M. H. Reddy, S. Jandhyala
{"title":"A comparative study of 6T-SRAM cell designed using Symmetrical Double Gate MOSFET and Symmetrical Double Gate Ferroelectric FET","authors":"M. H. Reddy, S. Jandhyala","doi":"10.1109/PRIMEASIA.2015.7450468","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450468","url":null,"abstract":"Scaling is aggressively performed for SRAMs to improve the memory integration density. At advanced technology nodes, 6T-SRAM cells built using Symmetrical Double Gate (SDG) MOSFETs are shown to perform better than those built with bulk MOSFETs. Recently the Symmetric Double-Gate Ferroelectric Field Effect Transistor (SDG-FeFET) has generated considerable interest since it has the potential to reduce the Subthreshold Swing (SS) of a transistor below the classical Boltzmann's limit. This was achieved exploiting the negative capacitance behavior of Ferroelectric Material which resulted in reduction of the power and delay of the transistor. In this paper, we simulate a 6T-SRAM cell using SDG-FeFETs and do the comparative study of its performance with SDG MOSFETs as a function of supply voltage and cell ratios. 6T-SRAM cell using SDG-FeFETs is shown to offer significant improvement in the read and write access times and marginal improvement in corresponding static noise margins (SNMs) as well, making it a attractive option for future technology nodes.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126207723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and simulation of programmable band-gap reference circuit 可编程带隙参考电路的设计与仿真
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450472
Mohd Ziauddin Jahangir, P. Chandrasekhar, N. V. Koteswara Rao
{"title":"Design and simulation of programmable band-gap reference circuit","authors":"Mohd Ziauddin Jahangir, P. Chandrasekhar, N. V. Koteswara Rao","doi":"10.1109/PRIMEASIA.2015.7450472","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450472","url":null,"abstract":"Band-gap voltage reference circuits are used to provide an independent reference voltage, which remains immune to power supply, temperature. One of the limitations of these circuits is they provide a single, unique value of voltage which is stable. Any effort to change this value will make the circuit voltage, temperature dependent. The voltage will be constant only for one voltage value and varies for other voltage values. In this work, we propose, a new circuit for generation of temperature and power supply independent, reference voltages which can be changed digitally. The best part of this circuit is, each output voltage value developed using this circuit, remains constant over a wide temperature range of -60° C to 120° C. This circuit generates four such voltages. The required value can be selected by using 3 different control lines.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125157769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
DCT and CORDIC on a novel configurable hardware 一种新型可配置硬件上的DCT和CORDIC
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450469
Nupur Jain, B. Mishra
{"title":"DCT and CORDIC on a novel configurable hardware","authors":"Nupur Jain, B. Mishra","doi":"10.1109/PRIMEASIA.2015.7450469","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450469","url":null,"abstract":"Discrete Cosine Transform (DCT) operations, used in compression algorithm, have great significance in image and signal processing applications where the cosine computation forms an integral part. The CORDIC (COrdinated Rotation Digital Computer) algorithm provides a simplistic and accurate platform to compute various trigonometric, linear and non-linear functions using only shift-add operations. Due to inherently repetitive nature of DCT and CORDIC function, it yields to efficient hardware implementations. This paper presents the implementation of DCT and CORDIC on a novel configurable architecture ported onto a state of the art FPGA. The proposed architecture uses only shifts and adds to perform multiplication, thereby reducing the gate count. The design takes 192 clock cycles and 336 clock cycles/image block to compute cosine using CORDIC and DCT, respectively. The L2 norm of the hardware reconstructed image is 15.77 at 84.37% compression on a 128×128 image and computes cosine (CORDIC) with accuracy upto 98%.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127730752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
1.2 mW 2.4 GHz PLL for ZigBee and BLE standard in single-well 0.18 µm CMOS with efficient divider architecture 1.2 mW 2.4 GHz锁相环，用于ZigBee和BLE标准，单孔0.18µm CMOS，具有高效分频架构
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450462
Purushothama Chary P, Rizwan Shaik Peerla, Sesha Sairam Regulagadda, M. A. Naseeb, A. Acharyya, P. Rajalaksmi, Debashis Mandal, A. Dutta
{"title":"1.2 mW 2.4 GHz PLL for ZigBee and BLE standard in single-well 0.18 µm CMOS with efficient divider architecture","authors":"Purushothama Chary P, Rizwan Shaik Peerla, Sesha Sairam Regulagadda, M. A. Naseeb, A. Acharyya, P. Rajalaksmi, Debashis Mandal, A. Dutta","doi":"10.1109/PRIMEASIA.2015.7450462","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450462","url":null,"abstract":"This paper proposes a novel single-well VCO in PLL architecture targeting ZigBee (ZB) and Bluetooth LE (BLE) band. It employs PMOS based charge recycling technique in Voltage Controlled Oscillator (VCO) and a Current Mode Logic (CML) divider for I-Q generation in single-well CMOS. An efficient, low current, Integer-N, Multi Modulus Divider (MMD) using True Single Phase Clock (TSPC) logic is incorporated in the design to minimize the overall PLL power consumption. The VCO-CML cell gives phase noise of -147 dBc/Hz at 1 MHz offset. PLL consumes 1.2mW of power at 1.2V supply with a settling time less than 45μs and core area is 743μm × 416μm using UMC 0.18μm CMOS Mixed Mode Technology.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"28 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116636603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A design of 2nd order DT sigma-delta modulator for medical implants 用于医疗植入物的二阶DT σ - δ调制器设计
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450460
M. Raheem, K. M. Chari, Mohammed Arifuddin Sohel, M. A. Mushahhid Majeed
{"title":"A design of 2nd order DT sigma-delta modulator for medical implants","authors":"M. Raheem, K. M. Chari, Mohammed Arifuddin Sohel, M. A. Mushahhid Majeed","doi":"10.1109/PRIMEASIA.2015.7450460","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450460","url":null,"abstract":"This paper proposes the design of a second order sigma delta modulator (SDM) to be used in medical implants for conversion of low frequency human body analog signals into digital format. The lifetime of a medical implant is governed by the power consumed by various blocks in it, of which the block consuming maximum power is the Analog to Digital Converter (ADC). This paper aims at designing a power optimized ADC by making use of CMOS operational trans-conductance amplifier(OTA) whose transistors are biased in sub threshold conduction region by making use of body biasing technique. The modulator thus implemented consumes a power of 4.6 μW from a 0.9V power supply. The modulator achieves an SNR of 64dB for a bandwidth of 500 Hz.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130404117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Clutter reduction using background subtraction of Ground Penetrating Radar for landmine detection 基于背景减法的探地雷达杂波抑制
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450461
N. Smitha, Vipula Singh
{"title":"Clutter reduction using background subtraction of Ground Penetrating Radar for landmine detection","authors":"N. Smitha, Vipula Singh","doi":"10.1109/PRIMEASIA.2015.7450461","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450461","url":null,"abstract":"GPR (Ground Penetrating Radar) is an application of electromagnetics that has been widely gaining momentum for the detection of landmines. Existing transmitter-receiver systems suffer from high background clutter, high false alarm rate and strong reflections from the air soil interface. Although many approaches have been developed, implementing them in man portable system is not practical. Our paper aims at developing and testing a viable signal processing methodology to address these issues. The signal processing technique considered is background subtraction in spatial domain. The major advantage of the approach is treating the raw data as images instead of s-parameter matrices. Three kinds of filters are used, namely averaging, thresholding and localization filter. The algorithms for filter implementations are simple and can be easily incorporated in DSPs. The B-scan data required for testing was simulated by considering frequency in the range 1-1.5GHz with soil permittivity. Considering various cases simulations are carried out using MatLab to reduce clutter using cascaded filter as a background subtraction approach.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131356566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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