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2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)最新文献

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A five level cascaded H-bridge multilevel STATCOM 一个五级级联h桥多电平STATCOM
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450466
C. L. Reddy, M. Sushama, P. Kumar, N. N. V. Surendra Babu
{"title":"A five level cascaded H-bridge multilevel STATCOM","authors":"C. L. Reddy, M. Sushama, P. Kumar, N. N. V. Surendra Babu","doi":"10.1109/PRIMEASIA.2015.7450466","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450466","url":null,"abstract":"This paper describes a three-phase cascade Static Synchronous Compensator (STATCOM) without transformer. It presents a control algorithm that meets the demand of load reactive power and also voltage balancing of isolated dc capacitors for H-bridges. The control algorithm used for inverter in this paper is based on a phase shifted carrier (PSC) modulation strategy that has no restriction on the cascaded number. The performance of the STATCOM for different changes of loads was simulated.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126904736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Tunnel transistors with circuit co-design in designing reliable logic gates for energy efficient computing 隧道晶体管与电路协同设计在设计可靠的节能计算逻辑门中的应用
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450475
Sadulla Shaik, K. Krishna, R. Vaddi
{"title":"Tunnel transistors with circuit co-design in designing reliable logic gates for energy efficient computing","authors":"Sadulla Shaik, K. Krishna, R. Vaddi","doi":"10.1109/PRIMEASIA.2015.7450475","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450475","url":null,"abstract":"Tunnel FETs have attracted much attention recently for energy efficient designs. This paper presents design, analysis and benchmarking of Tunnel FET (TFET) based reliable XOR logic gates with circuit co-design for energy efficient computing at scaled supply voltages (0.1-0.3V). A specific variant of TFET ie., homo-junction TFET (where source and drain are doped with same material InGaAs) has been explored and at the circuit level three XOR gate topologies such as 12T, 8T and 6T have been proposed. For benchmarking, 20nm double-gate FinFET technology has been used for all the designs. In FinFET designs, it has been demonstrated that 12T design is more robust and reliable (in terms of full swing) and less energy efficient and 6T design is most energy efficient, but reduced reliability. We demonstrate that TFET's' steep slope characteristics enable the 12T design to be energy efficient option along with improved reliability and 6T design is the best in terms of energy efficiency and reliability amongst all designs at 0.1V VDD.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126086324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Verilog implementation of adaptive compression of RGB images at low bit rates Verilog实现了RGB图像在低比特率下的自适应压缩
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450484
T. Arjun, Pranose J. Edavoor, S. Raveendran, K. P. Sumesh, Y. Nithin Kumar, M. H. Vasantha, Dheeraj Sharma
{"title":"Verilog implementation of adaptive compression of RGB images at low bit rates","authors":"T. Arjun, Pranose J. Edavoor, S. Raveendran, K. P. Sumesh, Y. Nithin Kumar, M. H. Vasantha, Dheeraj Sharma","doi":"10.1109/PRIMEASIA.2015.7450484","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450484","url":null,"abstract":"To meet the ever increasing demand for transferring image and video data in present day communication system without compromising the speed, either the channel bandwidth has to be increased or the total data traffic has to be decreased. As small screen devices and chat applications do not need original quality images to be reconstructed, certain relaxation on the quality of image is allowed if the total data traffic can be reduced to a great extent. Due to this reducing the size of the image to be sent by transforming it to a sparse domain, followed by decoding to retain the required quality has emerged as a solution. Verilog implementation of the proposed algorithm gives permission to the user to set the quality of the image to be reconstructed (by defining PSNR value) and allows the user to set the required compression by assigning the value of bits per pixel(bpp).","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129041269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Implementation of turbo codes using verilog-HDL and estimation of its error correction capability 用verilog-HDL实现turbo码并估计其纠错能力
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450473
Tepoju Vivek Vardhan, B. Neeraja, B. P. Kumar, C. Paidimarry
{"title":"Implementation of turbo codes using verilog-HDL and estimation of its error correction capability","authors":"Tepoju Vivek Vardhan, B. Neeraja, B. P. Kumar, C. Paidimarry","doi":"10.1109/PRIMEASIA.2015.7450473","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450473","url":null,"abstract":"Turbo coding is a powerful error correction technique among forward error correcting codes. Its performance is better as it achieves near Shannon limit. This paper presents the implementation of Turbo codec for designing the Turbo encoder and decoder. The Decoder is developed based on Viterbi algorithm that incorporates hard-input and hard-output values. The errors are purposefully introduced in the encoded data to estimate error correction capability. In such case, developed Turbo decoder is able to correct two bit error in the encoded data. The Encoder and Decoder of Turbo codec are implemented using Verilog-HDL. The code is ported in FPGA for real time verification.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125118310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Design of current reuse based Differential Merged LNA-Mixer (DMLNAM) and two-stage Dual Band LNA with two gain modes in 65nm technology 基于当前复用的差分合并LNA混频器(DMLNAM)和65nm双增益模式双级双频段LNA的设计
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450478
M. Kumar, Sesha Sairam Regulagadda, J. K. Das, A. Dutta
{"title":"Design of current reuse based Differential Merged LNA-Mixer (DMLNAM) and two-stage Dual Band LNA with two gain modes in 65nm technology","authors":"M. Kumar, Sesha Sairam Regulagadda, J. K. Das, A. Dutta","doi":"10.1109/PRIMEASIA.2015.7450478","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450478","url":null,"abstract":"In the radio frequency (RF) front-end, LNA with good noise figure without degrading performance a very important component to be developed. This paper presents design of two topologies of current reuse based Low Noise Amplifier (LNA) with low noise figure. LNA1 describe the fully integrated narrow band Differential Merged LNA-Mixer (DMLNAM) with two current reuse paths and LNA2 describes fully integrated Two stage Dual Band Low Noise Amplifier (DB-LNA) for 1.8GHz and 2.4GHz with two gain modes (high gain mode, low gain mode) in 65nm technology. The proposed DMLNAM(LNA1) employ first current reuse path to achieve low power, high gain and low noise figure and second current reuse path for narrow band load tuning and gm stage of Mixer is stacked on the top of CMOS LNA. In the proposed Two stage DB-LNA(LNA2), first stage employs a varactor for dual band input matching with self-biasing technique, current reuse structure to achieve high gain, low noise figure and low power consumption. Second stage employs current splitting technique to switch between two gain modes. Differential Merged LNA-Mixer features gain of 26.64dB with noise figure of 1.61dB@10MHz, 1.62dB@1MHz and 1.77dB@100KHz. In high gain mode (SW1=0V) of Two-stage Dual band LNA(LNA2) with two gain modes have a gain of 21.1dB, 19.61dB with a noise figure of 1.739dB, 2.22dB at 1.8GHz and 2.4GHz respectively. In low gain mode (SW1=1.2V), the Two stage DB-LNA features a gain of 12.15dB and 10.6dB and a noise figure of 2.36dB and 3.51dB at 1.8GHz and 2.4GHz respectively. The DMLNAM (LNA1) and Two stage DB-LNA circuit consumes 16.5mW@1.5V and 11mW@1.2V respectively.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"47 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123171413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Current mode biquadratic universal filter 电流型双二次型通用滤波器
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450467
A. Kushwaha, S. K. Paul
{"title":"Current mode biquadratic universal filter","authors":"A. Kushwaha, S. K. Paul","doi":"10.1109/PRIMEASIA.2015.7450467","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450467","url":null,"abstract":"A current mode universal filter using current controlled differential difference current conveyor transconductance amplifier (CCDDCCTA) is discussed. The filter provides important and desirable features : (i) Uses only one CCDDCCTA and two capacitors, (ii) One can get low pass (LP), band pass (BP), high pass (HP), notch (NF) and all pass (AP) current responses using the same configuration without any alteration, (iii) Passive components are grounded, which eases the integrated circuit implementation, (iv) Responses are electronically tunable, and (v) Sensitivity is low. Simulation results agree well with theory.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128196386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Characterization of BE-SONOS flash memory using rare-earth materials in tunnel barrier with improved memory dynamics 利用稀土材料改进隧道势垒中BE-SONOS快闪存储器的表征
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450459
Mansimran Kaur, Deepika Gupta, V. Vijayvargiya, S. Vishvakarma, V. Neema
{"title":"Characterization of BE-SONOS flash memory using rare-earth materials in tunnel barrier with improved memory dynamics","authors":"Mansimran Kaur, Deepika Gupta, V. Vijayvargiya, S. Vishvakarma, V. Neema","doi":"10.1109/PRIMEASIA.2015.7450459","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450459","url":null,"abstract":"In this paper, we have investigated the effect of rare-earth materials in tunnel dielectric to improve the trade-off between erase speed and retention. Here, rare-earth materials have low valence band offset with high permittivity to enhance both erase speed and retention in bandgap engineered silicon-oxide-nitride-oxide-silicon (BE-SONOS). In addition, we observed higher program speed due to lower conduction band offset as compared to SiO2. Silicate of scandate of rare earth element, GdScSiO (Gd=Gadolinium), is investigated as SiN replacement in tunnel dielectric (SiO2/SiN/SiO2) of BE-SONOS. Further, rare earth aluminates, GdAlO and LuAlO (Lu=Lutetium), are used to replace the SiO2 layer in tunnel oxide. Also, gate length is scaled down and we have observed the effect of aforementioned materials in tunnel barrier, however, for the same effective oxide thickness (EOT). We found that the scaling down of gate length has negligible impact on the reliability of the devices. As a consequence, various investigated tunnel oxide stacks possess good memory characteristics with a negligible charge loss (at 25 °C) after a period of ten years and a considerable charge loss at an elevated temperature of 150 °C.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"106 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113970585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling and design of 700W digital average current mode controlled multiphase bidirectional DC-DC converter 700W数字平均电流模式控制多相双向DC-DC变换器的建模与设计
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450486
K. Suryanarayana, H. Nagaraja
{"title":"Modeling and design of 700W digital average current mode controlled multiphase bidirectional DC-DC converter","authors":"K. Suryanarayana, H. Nagaraja","doi":"10.1109/PRIMEASIA.2015.7450486","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450486","url":null,"abstract":"Mathematical modeling and analysis of converters is an essential and critical phase in the design stage of the system. High current switching and inductor ripple causes electromagnetic interference in the system. Paralleling of the converters and smart switching control will reduce the stress on the converter switches. Substantial ripple reduction in the source and load current can be achieved by optimally choosing the transfer ratio. Multiphase technique increases the ripple frequency resulting in lesser filter requirements. A two phase bidirectional converter operating in continuous current conduction mode is modeled and digital average current mode control technique is proposed to regulate the output voltage. A 700 watt system is designed and the simulation and experimental results are presented.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121876968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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