2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)最新文献

An improved block based EZW technique for low dynamic range image compression 一种改进的基于块的EZW技术用于低动态范围图像压缩

2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450471

Ch. Naveen, V. Satpute, A. Keskar

{"title":"An improved block based EZW technique for low dynamic range image compression","authors":"Ch. Naveen, V. Satpute, A. Keskar","doi":"10.1109/PRIMEASIA.2015.7450471","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450471","url":null,"abstract":"This papers deals with improved image compression technique for images having low dynamic range. It is a well known fact that the dynamic range of the images having low intensity variations is less. So by considering this fundamental characteristic into account we can go for image compression at higher ratio with small modifications to the existing algorithms. To achieve the higher compression ratio, block-wise Embedded Zero Wavelet (EZW) is applied on the images by forcing all the blocks in the image to take the same number of dominant and sub-ordinate passes. The number of passes applied on each block of the image will be equal to the lowest number of passes taken by one of the blocks in image. This downside the number of passes applied on the image which reduces the number of bits used for encoding the image which successively increase the compression ratio. The proposed algorithm is analyzed with respect to the normal block-wise EZW by mathematical parameters and visual quality. The mathematical parameters chosen for comparison are Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity (SSIM) index.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123257133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An area efficient Q-format multiplier with high performance for digital processing applications 一种面积高效的q格式乘法器，具有高性能的数字处理应用

2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450485

V. K. Rao, K. Lavanya

{"title":"An area efficient Q-format multiplier with high performance for digital processing applications","authors":"V. K. Rao, K. Lavanya","doi":"10.1109/PRIMEASIA.2015.7450485","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450485","url":null,"abstract":"There has always been a quest going on for improving the performance of the multiplier as it is the key component in determining the performance of the digital signal processor. The Q-format multiplier implemented with Urdhva Triyagbhyam sutra of Vedic mathematics proved to be faster and area efficient. Yet, a further quest for increasing the performance of the Q-format multiplier resulted in the outcome of this paper. This paper presents a novel method using Booth encoding towards generation of reduced number of partial products and redundant binary adder for adding these partial products for implementation of 64 bit Q-format signed multiplier which substantially improved the performance by 22.60%, area reduced by 19.20%. This method has also been implemented for 16 bit and 32 bit multipliers along with 64 bit Q-format signed multiplier using Booth encoding and RB addition in VHDL targeted towards Xilinx FPGA Virtex-7 and results compared with those obtained by using Vedic Urdhva Triyagbhyam Sutra with CLA and found to have significant improvement in performance.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"151 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123497275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Analysis of TCR as a reactive power compensator TCR作为无功补偿器的分析

2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450481

M. Imran, S. Azeez

引用次数: 3

H-shaped microstrip antenna for broadband communications at 60 GHz 用于60 GHz宽带通信的h形微带天线

2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450474

A. Mehta, R. Ramer, L. Gong, S. Sachdeva

引用次数: 2

Stimulation driver circuits for non rectangular stimuli in biomedical implants 生物医学植入物中非矩形刺激的刺激驱动电路

2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450482

C. Rathna

引用次数: 0

A novel FPGA based digital octa-rate clock and data recovery circuit 一种新型的基于FPGA的数字八位数时钟和数据恢复电路

2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450470

Burugula Sai Sankalp, N. Reddy, B. P. Kumar, C. Paidimarry

{"title":"A novel FPGA based digital octa-rate clock and data recovery circuit","authors":"Burugula Sai Sankalp, N. Reddy, B. P. Kumar, C. Paidimarry","doi":"10.1109/PRIMEASIA.2015.7450470","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2015.7450470","url":null,"abstract":"Clock and data recovery (CDR) circuit in general, plays a vital role for serial-link communication in multi-module based System on chip (SOC). It uses a high frequency clock to handle high data rate, which results in high dynamic power consumption. In order to reduce the high dynamic power consumption, the proposed design works at the one-eighth frequency of the received data rate and presents a novel digital octa-rate clock and data recovery circuit as an optimal solution. The octa-rate CDR circuit consists of 16-phases generator, delay line controller, an octa-rate early-late type phase detector and digitally controlled delay line. The purpose of delay line controller is to provide sufficient delay in digitally controlled delay line. It is observed from literature that the existing delay line controller is realized by using combinational circuit which is not providing sufficient delay. Hence, in this work we introduced Finite State Machine (FSM) based delay line controller to provide sufficient delay. In order to reduce dynamic power consumption, a novel octa-rate CDR circuit has been realized using Xilinx ISE 13.2 and implemented on Vertex-5 FPGA target device for real time verification. Corresponding results shows a significant dynamic power reduction.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117302725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Charge pump circuit with improved absolute current deviation and increased dynamic output voltage range across PVT variations 电荷泵电路改善了绝对电流偏差，增加了PVT变化的动态输出电压范围

2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450465

Suraj Gupta, S. A. Mondal, H. Rahaman

引用次数: 1

Solar-powered spike-based communication system with analog back scatter 具有模拟反向散射的太阳能尖峰通信系统

2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450483

Javed S. Gaggatur, M. Machnoor

引用次数: 6

Ultra low power 128 byte memory design based on D-Latch in 0.18 µm process 基于0.18µm工艺D-Latch的超低功耗128字节存储器设计

2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450476

Saurabh Tripathi, Nupur Jain, B. Mishra

引用次数: 0

A 43-nW 10-bit 1-kS/s SAR ADC in 180nm CMOS for biomedical applications 43-nW 10位1-kS/s SAR ADC, 180nm CMOS，用于生物医学应用

2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI: 10.1109/PRIMEASIA.2015.7450463

Kunal Yadav, P. Patra, A. Dutta

引用次数: 6