Ultra low power 128 byte memory design based on D-Latch in 0.18 µm process

Abstract

This work mainly presents a novel 128 byte full custom memory array based on D-Latch. A robust full custom read write memory architecture is proposed that is best suited to operate in the sub-threshold region. Starting with different latch architectures minimum operating supply voltage comparison, the complete byte addressable memory design has been discussed. We further analyse the performance results under an application and its different parameters. All the design parameters and the simulation results are presented for 0.18 μm process.