1.2 mW 2.4 GHz PLL for ZigBee and BLE standard in single-well 0.18 µm CMOS with efficient divider architecture

Abstract

This paper proposes a novel single-well VCO in PLL architecture targeting ZigBee (ZB) and Bluetooth LE (BLE) band. It employs PMOS based charge recycling technique in Voltage Controlled Oscillator (VCO) and a Current Mode Logic (CML) divider for I-Q generation in single-well CMOS. An efficient, low current, Integer-N, Multi Modulus Divider (MMD) using True Single Phase Clock (TSPC) logic is incorporated in the design to minimize the overall PLL power consumption. The VCO-CML cell gives phase noise of -147 dBc/Hz at 1 MHz offset. PLL consumes 1.2mW of power at 1.2V supply with a settling time less than 45μs and core area is 743μm × 416μm using UMC 0.18μm CMOS Mixed Mode Technology.