一种用于宽带多位adc的低硬件复杂度时域量化器

2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2015-11-01 DOI:10.1109/PRIMEASIA.2015.7450479

P. Jha, P. Patra, A. Dutta

{"title":"一种用于宽带多位adc的低硬件复杂度时域量化器","authors":"P. Jha, P. Patra, A. Dutta","doi":"10.1109/PRIMEASIA.2015.7450479","DOIUrl":null,"url":null,"abstract":"This paper presents proof of concept of a low hardware complexity time domain quantizer (TDQ) for wideband multibit countinuous time (CT) ΣΔ ADCs. Besides rendering multi-level quantization of the input signal, the proposed scheme generates a two-level loop feedback signal for the modulator. The two-level feedback eliminates the errors emanating from component mismatches in the feedback digital-to-analog converter (DAC) due to process variations. The complete scheme is modeled using Simulink (MATLAB) and is validated through simulation. A 2nd order ΣΔ modulator incorporating the proposed TDQ achieves a dynamic range of 45.7 dB for a bandwidth of 10 MHz and an input sine-wave of -5.78 dBFS amplitude.","PeriodicalId":137621,"journal":{"name":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A low hardware complexity time domain quantizer for wideband multibit - ADCs\",\"authors\":\"P. Jha, P. Patra, A. Dutta\",\"doi\":\"10.1109/PRIMEASIA.2015.7450479\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents proof of concept of a low hardware complexity time domain quantizer (TDQ) for wideband multibit countinuous time (CT) ΣΔ ADCs. Besides rendering multi-level quantization of the input signal, the proposed scheme generates a two-level loop feedback signal for the modulator. The two-level feedback eliminates the errors emanating from component mismatches in the feedback digital-to-analog converter (DAC) due to process variations. The complete scheme is modeled using Simulink (MATLAB) and is validated through simulation. A 2nd order ΣΔ modulator incorporating the proposed TDQ achieves a dynamic range of 45.7 dB for a bandwidth of 10 MHz and an input sine-wave of -5.78 dBFS amplitude.\",\"PeriodicalId\":137621,\"journal\":{\"name\":\"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PRIMEASIA.2015.7450479\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PRIMEASIA.2015.7450479","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文提出了一种用于宽带多位连续时间(CT) ΣΔ adc的低硬件复杂度时域量化器(TDQ)的概念证明。除了实现输入信号的多级量化外，该方案还为调制器生成一个两级环路反馈信号。双电平反馈消除了由于工艺变化而导致的反馈数模转换器(DAC)中元件不匹配所产生的误差。利用Simulink (MATLAB)对整个方案进行了建模，并通过仿真进行了验证。采用该TDQ的二阶ΣΔ调制器在带宽为10 MHz时可实现45.7 dB的动态范围，输入正弦波振幅为-5.78 dBFS。

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A low hardware complexity time domain quantizer for wideband multibit - ADCs

This paper presents proof of concept of a low hardware complexity time domain quantizer (TDQ) for wideband multibit countinuous time (CT) ΣΔ ADCs. Besides rendering multi-level quantization of the input signal, the proposed scheme generates a two-level loop feedback signal for the modulator. The two-level feedback eliminates the errors emanating from component mismatches in the feedback digital-to-analog converter (DAC) due to process variations. The complete scheme is modeled using Simulink (MATLAB) and is validated through simulation. A 2nd order ΣΔ modulator incorporating the proposed TDQ achieves a dynamic range of 45.7 dB for a bandwidth of 10 MHz and an input sine-wave of -5.78 dBFS amplitude.

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2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)

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