T. Ostermann, C. Lackner, R. Koessl, R. Hagelauer, K. Beer, L. Krahn, H-T. Mammen, W. John, A. Sauer, P. Schwarz, G. Elst, M. Pistauer
{"title":"LIMA: The new e-Learning platform in microelectronic applications","authors":"T. Ostermann, C. Lackner, R. Koessl, R. Hagelauer, K. Beer, L. Krahn, H-T. Mammen, W. John, A. Sauer, P. Schwarz, G. Elst, M. Pistauer","doi":"10.1109/MSE.2003.1205280","DOIUrl":"https://doi.org/10.1109/MSE.2003.1205280","url":null,"abstract":"We present the new e-Learning platform LIMA, a fully web-based training platform which deals with the three course topics \"Virtual EMC Lab\", \"Advanced RF Design Center\" and \"Mixed-signal Simulation Center, based on VHDL-AMS\". It is essential for state of the art design in information and communication technology to provide excellent teaching material in this areas of interest. The web-based training platform could be used for graduate students as well as designers in the industry to obtain and maintain high qualified knowledge.","PeriodicalId":137611,"journal":{"name":"Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132951190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SIFU!-a didactic stuck-at fault simulator","authors":"Vinícius P. Correia, M. Lubaszewski, A. Reis","doi":"10.1109/MSE.2003.1205270","DOIUrl":"https://doi.org/10.1109/MSE.2003.1205270","url":null,"abstract":"This paper presents a didactic simulator for stuck-at (sa) faults on logic circuits. The tool has a set of features that helps to understand the concepts of single and multiple stuck-at faults, being these faults testable or not, and how to generate test vectors in order to test the detectable fault subset. An interface was developed to allow the edition of a circuit, the injection of faults and the fault simulation. The tool performs two simulations concurrently, one for the original circuit and another for the faulty circuit considering the injected faults. When the two simulations differ, for a given input vector, the tool shows the error (detection of the fault) graphically.","PeriodicalId":137611,"journal":{"name":"Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117116697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Introducing the concept of design reuse into undergraduate digital design curriculum","authors":"G. Qu","doi":"10.1109/MSE.2003.1205231","DOIUrl":"https://doi.org/10.1109/MSE.2003.1205231","url":null,"abstract":"Intellectual property (IP) reuse based system design is becoming an industry standard recently. However, current educational system is not effective in the training of engineers who design by reuse and design for reuse. In this paper, we report our experience at the University of Maryland at College Park (UMCP) in introducing the concept of design reuse into the introductory digital logic design course. We present a practical curriculum innovation plan, which does not increase the teaching load or sacrifices the current curriculum significantly, to implement this idea. Our teaching experience show that students learn the basics of design reuse and enjoy doing IP-based design.","PeriodicalId":137611,"journal":{"name":"Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03","volume":"650 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116092551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Bertrand, M. Flottes, L. Balado, J. Figueras, Anton Biasizzo, F. Novak, S. Carlo, P. Prinetto, N. Pricopi, H. Wunderlich, J. V. D. Heyden
{"title":"Test engineering education in Europe: the EuNICE-Test project","authors":"Y. Bertrand, M. Flottes, L. Balado, J. Figueras, Anton Biasizzo, F. Novak, S. Carlo, P. Prinetto, N. Pricopi, H. Wunderlich, J. V. D. Heyden","doi":"10.1109/MSE.2003.1205266","DOIUrl":"https://doi.org/10.1109/MSE.2003.1205266","url":null,"abstract":"The paper deals with a European experience of education in industrial test of ICs and SoCs using remote testing facilities. The project addresses the problem of the shortage in microelectronics engineers aware with the new challenge of testing mixed-signal SoCs far multimedia/telecom market. It aims at providing test training facilities at a European scale in both initial and continuing education contexts. This is done by allowing the academic and industrial partners of the consortium to train engineers using the common test resources center (CRTC) hosted by LIRMM (Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier, France). CRTC test tools include up-to-date/high-tech testers that are fully representative of real industrial testers as used on production testfloors. At the end of the project, it is aimed at reaching a cruising speed of about 16 trainees per year per center. Each trainee will have attend at least one one-week training using the remote test facilities of CRTC.","PeriodicalId":137611,"journal":{"name":"Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125921502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Hedberg, T. Lenart, Henrik Svensson, P. Nilsson, V. Öwall
{"title":"Teaching digital HW-design by implementing a complete MP3 decoder","authors":"H. Hedberg, T. Lenart, Henrik Svensson, P. Nilsson, V. Öwall","doi":"10.1109/MSE.2003.1205241","DOIUrl":"https://doi.org/10.1109/MSE.2003.1205241","url":null,"abstract":"This paper describes a project course that focuses on all the different stages in an ASIC design flow. The project starts at algorithm level, followed by architecture selection, netlist generation, down to physical layout, fabrication, and finally verification. The scope of the project, implementing a complete MP3 decoder in VHDL and sending it for fabrication, motivates the students to work hard towards a common goal.","PeriodicalId":137611,"journal":{"name":"Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126544072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Industry needs and expectations of SoC design education","authors":"G. Martin","doi":"10.1109/MSE.2003.1205292","DOIUrl":"https://doi.org/10.1109/MSE.2003.1205292","url":null,"abstract":"Universities are currently updating their VLSI design education offerings to cover the important needs of System-on-Chip (SoC) design. It is important to recognize that SoC is a qualitative shift in design practice: not just more of the same things, for larger and larger designs, but a need to emphasise new topics and a more systematic approach to the design process. SoC is as much or more 'System' than 'Chip': thus topics such as embedded software, system-level design, algorithmic design, IP design and IP integration must be added to the curriculum. Verification, and new verification concepts, methods, languages and tools for IP development and integration need a special emphasis. In the new curriculum, design methods, processes and flows become as or more important than basic tool mechanics, and the relationship of standards and technical-business issues which affect SoC, such as IP packaging, qualification, evaluation, acquisition, and exchange are all topics to which students should have a basic exposure.","PeriodicalId":137611,"journal":{"name":"Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125234211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Incorporating EDA into the Rowan ECE curriculum","authors":"L. Head","doi":"10.1109/MSE.2003.1205273","DOIUrl":"https://doi.org/10.1109/MSE.2003.1205273","url":null,"abstract":"This paper describes the Electronic Design Automation (EDA) environment at Rowan University's College of Engineering. The courses are summarized and an evaluation of the environment is presented.","PeriodicalId":137611,"journal":{"name":"Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131525876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Team project-an effective tool for application of knowledge and deriving engineering competencies","authors":"D. Donoval, D. Hajtas","doi":"10.1109/MSE.2003.1205253","DOIUrl":"https://doi.org/10.1109/MSE.2003.1205253","url":null,"abstract":"Wide theoretical background and engineering (professional and personal) competencies are the natural skills of new hire. Student individual and team projects provide a nice environment for best engineering practice. Introduction of the team projects requires the creation of teams of 4 to 5 students, and application of the obtained multidisciplinary knowledge. The enhancement of students' motivation for active participation in projects may be achieved by involvement of an industrial partner, either by bringing the real life projects or by various sponsorships provided to the university. The student competition and participation in the contest for the best student R&D work contribute considerably to the students' positive attitude to this form of education.","PeriodicalId":137611,"journal":{"name":"Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131775910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dynamic electrical characterization of CMOS-like thin film transistor circuits","authors":"G. Gautier, S. Crand, O. Bonnaud","doi":"10.1109/MSE.2003.1205233","DOIUrl":"https://doi.org/10.1109/MSE.2003.1205233","url":null,"abstract":"This tutorial is intended to graduate students, specialized in microelectronics formation. Before this work, the concerned students have spent one week in the cleanroom. In this training, with the help of teachers of the common microelectronics center, they processed and characterized a specific thin film transistor technology. The main goal was to set-up a bench that allows measuring dynamic parameters such as rise time, fall time and oscillator frequency directly on glass substrate and to analyze and explain the results on the base of classical modeling available for VLSI CMOS circuits.","PeriodicalId":137611,"journal":{"name":"Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121146595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Patricia Giacomelli, M. C. Schneider, C. Galup-Montoro
{"title":"MOSVIEW: a graphical tool for MOS analog design","authors":"Patricia Giacomelli, M. C. Schneider, C. Galup-Montoro","doi":"10.1109/MSE.2003.1205247","DOIUrl":"https://doi.org/10.1109/MSE.2003.1205247","url":null,"abstract":"This paper presents MOSVIEW, a graphical tool for transistor-level design of analog MOS circuits. MOSVIEW allows students to visualize and explore the design space in order to size and bias the transistor for a given set of specifications.","PeriodicalId":137611,"journal":{"name":"Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130622611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}