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Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03最新文献

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Teaching trade-offs in system-level design methodologies 教授系统级设计方法的权衡
Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03 Pub Date : 2003-06-01 DOI: 10.1109/MSE.2003.1205256
K. Sakiyama, P. Schaumont, D. Hwang, I. Verbauwhede
{"title":"Teaching trade-offs in system-level design methodologies","authors":"K. Sakiyama, P. Schaumont, D. Hwang, I. Verbauwhede","doi":"10.1109/MSE.2003.1205256","DOIUrl":"https://doi.org/10.1109/MSE.2003.1205256","url":null,"abstract":"This paper summarizes two graduate-level class projects in EE201A/EE298 (VLSI Architectures and Design Methods) at the University of California, Los Angeles (UCLA). The purpose of the class is to explore the impact of system-level optimization for various target platforms using EDA.","PeriodicalId":137611,"journal":{"name":"Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133850388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Internet-based tool for system-on-chip project testing and grading 基于互联网的系统芯片项目测试和评分工具
Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03 Pub Date : 2003-06-01 DOI: 10.1109/MSE.2003.1205282
Christopher K. Zuver, Christopher E. Neely, J. Lockwood
{"title":"Internet-based tool for system-on-chip project testing and grading","authors":"Christopher K. Zuver, Christopher E. Neely, J. Lockwood","doi":"10.1109/MSE.2003.1205282","DOIUrl":"https://doi.org/10.1109/MSE.2003.1205282","url":null,"abstract":"A tool has been developed to automate the testing and grading of design projects implemented in reprogrammable hardware. The server allows multiple students to test circuits in FPGA hardware over the internet. A web interface allows students to upload their placed and routed designs to the server, which batches the jobs together and (1) sequentially programs an FPGA board, (2) inputs test vectors, (3) generates a report that details the results, and (4) grades the design as either \"pass\" or \"fail.\" The single server allows an entire class to share the same FPGA board.","PeriodicalId":137611,"journal":{"name":"Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132727729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
RFIC loadpull simulations implementing best practice RF and mixed-signal design using an integrated agilent and cadence EDA tool 使用集成的agilent和cadence EDA工具实现最佳实践RF和混合信号设计的RFIC负载拉仿真
Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03 Pub Date : 2003-06-01 DOI: 10.1109/MSE.2003.1205262
J. Mukherjee, J. Parry, W. Dai, P. Roblin, S. Bibyk, Jongsoo Lee
{"title":"RFIC loadpull simulations implementing best practice RF and mixed-signal design using an integrated agilent and cadence EDA tool","authors":"J. Mukherjee, J. Parry, W. Dai, P. Roblin, S. Bibyk, Jongsoo Lee","doi":"10.1109/MSE.2003.1205262","DOIUrl":"https://doi.org/10.1109/MSE.2003.1205262","url":null,"abstract":"This paper describes the use of the newly developed Cadence to ADS dynamic link in loadpull simulations for BiCMOS RFIC design in a University environment. The process described here helps a designer achieve an integrated design environment where both RF design and traditional VLSI design principles can be applied in an integrated manner.","PeriodicalId":137611,"journal":{"name":"Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123447726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Teaching IP core development: an example 教学IP核开发:一个例子
Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03 Pub Date : 2003-06-01 DOI: 10.1109/MSE.2003.1205234
A. Milenković, David Fatzer
{"title":"Teaching IP core development: an example","authors":"A. Milenković, David Fatzer","doi":"10.1109/MSE.2003.1205234","DOIUrl":"https://doi.org/10.1109/MSE.2003.1205234","url":null,"abstract":"The increasing gap between design productivity and chip complexity, and emerging systems-on-a-chip (SoC) have led to the wide utilization of reusable intellectual property (IP) cores. Educators' responsibility is to provide future generations of SoC architects with knowledge necessary for successful design and use of IP cores, and to offer them a system perspective including both hardware and software. One way to accomplish this goal is through projects focused on soft CPU cores development. In this paper, we show the design flow and give the details of one such project aimed to develop a Microchip's PIC18 microcontroller core and implement it on an FPGA.","PeriodicalId":137611,"journal":{"name":"Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127934477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Extensive introduction to VHDL and PLDs in the sophomore year 二年级广泛介绍了VHDL和pld
Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03 Pub Date : 2003-06-01 DOI: 10.1109/MSE.2003.1205237
Eric W. Johnson
{"title":"Extensive introduction to VHDL and PLDs in the sophomore year","authors":"Eric W. Johnson","doi":"10.1109/MSE.2003.1205237","DOIUrl":"https://doi.org/10.1109/MSE.2003.1205237","url":null,"abstract":"As system courses move into the undergraduate curriculum, students must learn earlier how to create designs with hardware description languages (HDLs). A majority of current logic design textbooks, however, contain only supplemental sections on VHDL or Verilog. These sections, if covered by faculty, are usually integrated with the traditional logic design topics. While this methodology may work for some students, a majority can find it difficult to learn both logic design basics and a hardware description language at the same time. This paper describes a more extensive introduction to VHDL and programmable logic devices (PLDs) in the sophomore year through a second logic design course. By having this course early in the curriculum, students have been able to use their knowledge in upper-level microelectronics and systems courses, and have acquired quality internships after their sophomore year.","PeriodicalId":137611,"journal":{"name":"Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117007454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
VALID: custom ASIC verification and FPGA education platform 有效:自定义ASIC验证和FPGA教育平台
Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03 Pub Date : 2003-06-01 DOI: 10.1109/MSE.2003.1205257
P. Murphy, J. P. Frantz, E. Welsh, R. Hardy, T. Mohsenin, Joseph R. Cavallaro
{"title":"VALID: custom ASIC verification and FPGA education platform","authors":"P. Murphy, J. P. Frantz, E. Welsh, R. Hardy, T. Mohsenin, Joseph R. Cavallaro","doi":"10.1109/MSE.2003.1205257","DOIUrl":"https://doi.org/10.1109/MSE.2003.1205257","url":null,"abstract":"This paper describes VALID, a platform for testing student designed ASICs and for teaching the basics of FPGA design. VALID is designed to maximize ease of use from a student's perspective while maintaining enough flexibility for its use as an FPGA development and instruction platform. This system was designed entirely by students, has been successfully manufactured and is currently being used in a number of courses at Rice.","PeriodicalId":137611,"journal":{"name":"Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127761155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
TestosterICs: a low-cost functional chip tester 睾丸激素:一个低成本的功能芯片测试仪
Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03 Pub Date : 2003-06-01 DOI: 10.1109/MSE.2003.1205261
D. Harris, D. Diaz
{"title":"TestosterICs: a low-cost functional chip tester","authors":"D. Harris, D. Diaz","doi":"10.1109/MSE.2003.1205261","DOIUrl":"https://doi.org/10.1109/MSE.2003.1205261","url":null,"abstract":"Students in VLSI design courses find the opportunity to fabricate their chip designs very exciting and motivational. However, testing the chips after fabrication can be a hassle for both students and faculty. In collaboration with Sun Microsystems Laboratories, we have developed a functional chip tester that applies test vectors at low speed to check logical operation. The tester supports packages with up to 256 pins and operates over a range of 1.2-6.5 volts. It reads test vectors directly from IRSIM files and can be programmed through a Java API. The tester can also be used to drive scan chains and other control signals in conjunction with a high-speed signal generator and oscilloscope to test chips at speed. We have released the chip tester plans in open-source form and manufactured 20 units for other universities.","PeriodicalId":137611,"journal":{"name":"Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03","volume":"25 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113976447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A collaborative environment for remote experimentation 远程实验的协作环境
Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03 Pub Date : 1900-01-01 DOI: 10.1109/MSE.2003.1205254
M. Callaghan, J. Harkin, C. Peters, T. McGinnity, L. Maguire
{"title":"A collaborative environment for remote experimentation","authors":"M. Callaghan, J. Harkin, C. Peters, T. McGinnity, L. Maguire","doi":"10.1109/MSE.2003.1205254","DOIUrl":"https://doi.org/10.1109/MSE.2003.1205254","url":null,"abstract":"Embedded systems have become common place in industry and domestic electronics, resulting in the need for educational institutions to teach advanced embedded systems design. Experience in teaching engineering subjects has shown that a complementary approach combining theoretical and practical exercises is vital for effective learning. Increasingly, teaching institutions are offering remote access to distant laboratories as part of an overall e-learning strategy. However the majority of remote laboratories developed to date have suffered from a major deficiency, namely the provision of a web based environment that accurately recreates the experience of traditional campus based laboratories. This paper addresses these issues and presents a supported collaborative learning environment for remote experimentation.","PeriodicalId":137611,"journal":{"name":"Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126901050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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