2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)最新文献_第4页

A systematic study of lightweight hash functions on FPGAs fpga上轻量级哈希函数的系统研究

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032493

Bernhard Jungk, Leandro Rodrigues Lima, Matthias Hiller

引用次数: 18

Versatile educational and research robotic platform based on reconfigurable hardware 基于可重构硬件的多功能教育和研究机器人平台

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032564

Carlos Andres Lara-Nino, C. Torres-Huitzil, J. H. Barrón-Zambrano

{"title":"Versatile educational and research robotic platform based on reconfigurable hardware","authors":"Carlos Andres Lara-Nino, C. Torres-Huitzil, J. H. Barrón-Zambrano","doi":"10.1109/ReConFig.2014.7032564","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032564","url":null,"abstract":"This paper presents the development of a field-programmable gate array (FPGA)-based platform. This platform is intended for the community as an educational and efficient prototyping tool, in digital signal processing, robotics, and control, but it can also be used as to develop custom robotic architectures. The proposed platform centered around an FPGA device is embedded on an off-the-shelf Phoenix hexapod robot. The platform is equipped with a camera module targeted to real time computer vision. From an academic point of view, the main use for the developed platform is to be employed as a didactic resource that facilitates the understanding of theoretical concepts commonly used in engineering courses and to speed up the development cycle in hands-on practice. A set of software tools and low-level drivers have been developed to configure the vision sensor, transfer images to/from a computer and to manage the testing of image and digital processing and control tasks in a transparent way. To validate the platform a hardware vision architecture and a locomotion control module have been created. The high level control is performed in a soft-processor that simulates the Arduino ONE micro controller. The soft-processor takes information from the vision sensor to generate controls signals for a generic module able to take a digital input and deliver a pulse-width modulation (PWM) output.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"276 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114014381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Hardware/software infrastructure for ASIC commissioning and rapid system prototyping 用于ASIC调试和快速系统原型的硬件/软件基础设施

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032532

Peter Reichel, Jens Döge

引用次数: 3

Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures 粗粒度可重构架构中数据流图映射的强制定向调度

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032519

Alexander Fell, Z. Rákossy, A. Chattopadhyay

{"title":"Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures","authors":"Alexander Fell, Z. Rákossy, A. Chattopadhyay","doi":"10.1109/ReConFig.2014.7032519","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032519","url":null,"abstract":"In terms of energy and flexibility, Coarse-Grained Reconfigurable Architectures (CGRA) are proven to be advantageous over fine-grained architectures, massively parallel GPUs and generic CPUs. However the key challenge of programmability is preventing wide-spread adoption. To exploit instruction level parallelism inherent to such architectures, optimal scheduling and mapping of algorithmic kernels is essential. Transforming an input algorithm in the form of a Data Flow Graph (DFG) into a CGRA schedule and mapping configuration is very challenging, due the necessity to consider architectural details such as memory bandwidth requirements, communication patterns, pipelining and heterogeneity to optimally extract maximum performance. In this paper, an algorithm is proposed that employs Force-Directed Scheduling concepts to solve such scheduling and resource minimization problems. Our heuristic extensions are flexible enough for generic heterogeneous CGRAs, allowing to estimate the execution time of an algorithm with different configurations, while maximizing the utilization of available hardware. Beside our experiments, we compare also given CGRA configurations introduced by state-of-the-art mapping algorithms such as EPIMap, achieving optimal resource utilization by our schedule with a reduced overall DFG execution time by 39% on average.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116450192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Adaptive and reconfigurable fault-tolerant routing method for 2D Networks-on-Chip 二维片上网络的自适应可重构容错路由方法

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032494

Poona Bahrebar, D. Stroobandt

{"title":"Adaptive and reconfigurable fault-tolerant routing method for 2D Networks-on-Chip","authors":"Poona Bahrebar, D. Stroobandt","doi":"10.1109/ReConFig.2014.7032494","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032494","url":null,"abstract":"Networks-on-Chip (NoCs) are becoming more susceptible to faults due to the increasing density in the VLSI circuits. As a result, designing reliable and efficient routing methods is highly desirable. Most of the existing fault-tolerant routing techniques use nonminimal paths to reroute the packets around the faulty regions. Using these approaches, the network performance degrades drastically not only by taking unnecessary longer paths, but also by creating hotspots around the faults. Moreover, they are designed statically and cannot adapt to the dynamic traffic distribution in the network. In this paper, a reconfigurable and fault-tolerant routing method is proposed which is designed based on the Abacus Turn Model (AbTM). The presented deadlock-free routing technique is dynamically tuned based on the location of faults and congestion in the network. Thus, it is able to tolerate all single router failures without exploiting virtual channels. Moreover, it can grant full adaptiveness to the hotspot regions of the network. Using this scheme, the rerouting is minimized by forwarding the packets through the available shortest paths. This efficiency makes the proposed method a powerful asset for reliable routing in NoCs.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128095092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A device-agnostic tool for precomputing legal placements in modular design flows 一个设备不可知的工具，用于在模块化设计流程中预先计算合法位置

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032551

A. A. Sohanghpurwala, P. Athanas, A. Love

引用次数: 1

An AWF digital spectrometer for a radio telescope 用于射电望远镜的AWF数字光谱仪

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032503

Hiroki Nakahara, H. Nakanishi, K. Iwai

{"title":"An AWF digital spectrometer for a radio telescope","authors":"Hiroki Nakahara, H. Nakanishi, K. Iwai","doi":"10.1109/ReConFig.2014.7032503","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032503","url":null,"abstract":"A radio telescope analyzes radio frequency (RF) signal from celestial objects. It consists of an antenna, a receiver, and a spectrometer. The spectrometer converts signal in the time domain into one in the frequency domain by an FFT operation. In the conventional spectrometer, first, it multiples the window coefficient by the received signal. Second, it performs the FFT operation. Third, it converts the signal into the magnitude of the complex number. Finally, to reduce the noise, it accumulates obtained power spectrum. We call this a WFA spectrometer. Since the analog-to-digital converter (ADC) is faster than an FPGA, a parallel FFT computation is desired. However, since the number of on-chip memories for the FFT becomes the bottleneck, the conventional WFA spectrometer could not realize the wide-band and high-resolution. This paper proposes an AWF spectrometer which replaces the order of operations. Since the AWF spectrometer reduces the parallelism of the FFT, it is smaller than the conventional WFA spectrometer. Also, the AWF spectrometer can use a sequential FFT rather than the parallel one. It can be realized by an off-chip memory. Thus, it reduces the number of on-chip memories. Experimental results show that the proposed AWF spectrometer outperforms conventional WFA spectrometers.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121841117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Power analysis attack on hardware implementation of MAC-Keccak on FPGAs fpga上MAC-Keccak硬件实现的功耗分析攻击

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032549

Pei Luo, Yunsi Fei, Xin Fang, A. Ding, M. Leeser, D. Kaeli

引用次数: 15

Dynamic protocol stacks in smart camera networks 智能摄像机网络中的动态协议栈

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032511

M. Happe, Yujiao Huang, A. Keller

{"title":"Dynamic protocol stacks in smart camera networks","authors":"M. Happe, Yujiao Huang, A. Keller","doi":"10.1109/ReConFig.2014.7032511","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032511","url":null,"abstract":"The term Internet of Things is often used to talk about the trend of embedding microprocessors in everyday devices and connecting them to the Internet. The Internet of Things poses challenging communication requirements since the participating devices are heterogeneous, resource-constrained and operate in an ever changing environment. To cope with those requirements, academic research projects have proposed novel network architectures, such as the Dynamic Protocol Stack (DPS) architecture. In this paper, we use smart camera networks as an example of the Internet of Things and evaluate the DPS architecture in this scenario. Our smart camera nodes are implemented as an FPGA-based system-on-chip architecture that uses the DPS architecture for the network communication. We evaluate our smart camera nodes in two case studies. In the first case study, we demonstrate that our proposed smart camera network can track a single object over the field of view of several camera nodes. In the second case study, we show that an adaptive hardware/software mapping of the network functionality can save about 22% of the FPGA resources as compared to a static mapping. The hardware/software mapping can be adapted at a processing delay of a single video frame.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"277 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122261869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Advanced branch predictors for soft processors 用于软处理器的高级分支预测器

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032495

Di Wu, Andreas Moshovos

引用次数: 3