2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)最新文献

FPGA design and implementation of a matrix multiplier based accelerator for 3D EKF SLAM 基于矩阵乘法器的三维EKF SLAM加速器的FPGA设计与实现

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-08 DOI: 10.1109/ReConFig.2014.7032523

D. Tertei, J. Piat, M. Devy

{"title":"FPGA design and implementation of a matrix multiplier based accelerator for 3D EKF SLAM","authors":"D. Tertei, J. Piat, M. Devy","doi":"10.1109/ReConFig.2014.7032523","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032523","url":null,"abstract":"In hw/sw co-design FPGAs are being used in order to accelerate existing solutions so they meet real-time constraints. As they consume less power than a standard microprocessor and provide powerful parallel data processing capabilities, they remain a highly optimizable tool and object of research within an embedded system. In this paper we present an efficient architecture for matrix multiplication accelerator conceived as a systolic array co-processor to IBM's PPC440 processor on Virtex5 XC5VFX70T FPGA. Our design is afterwards synthesized and wired as a large-scale matrix multiplier required for an embedded version of a visual Simultaneous Localization and Mapping (SLAM) algorithm based on Extended Kaiman Filter (EKF). This algorithm is implemented entirely as a System On a programmable Chip (SoC) design on the FPGA; an EKF epoch is executed at least 7.3 times faster than the pure software implementation, maintaining and correcting 20 points in the map. This optimization permits an EKF block throughput to be increased from 6.07Hz to 44.39Hz, which exceeds our real-time constraint of 30Hz.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126679770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA 缺陷容忍技术对基于sram的集群FPGA网格临界性的影响

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-08 DOI: 10.1109/ReConFig.2014.7032508

Adrien Blanchardon, R. Chotin-Avot, H. Mehrez, Emna Amouri

引用次数: 0

Stochastically computing discrete Fourier transform with reconfigurable digital fabric 随机计算离散傅里叶变换的可重构数字结构

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032558

Yu Bai, Mingjie Lin

引用次数: 1

Data path analysis for dynamic circuit specialisation 数据路径分析的动态电路专业化

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032507

Tom Davidson, D. Stroobandt

引用次数: 0

FSM merging and reduction for IP cores watermarking using Genetic Algorithms 基于遗传算法的IP核水印FSM合并约简

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032525

Jorge Echavarria, A. Morales-Reyes, R. Cumplido, M. Salido

{"title":"FSM merging and reduction for IP cores watermarking using Genetic Algorithms","authors":"Jorge Echavarria, A. Morales-Reyes, R. Cumplido, M. Salido","doi":"10.1109/ReConFig.2014.7032525","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032525","url":null,"abstract":"This paper proposes an improved procedure to watermark soft Intellectual Property (IP) Cores at the Register Transfer Level (RTL) using Genetic Algorithms (GA). In order to merge the watermark signature and the IP Core's behavioral description, both are translated into Finite State Machines (FSM). The resulting FSM contains the watermarked IP Core maintaining its original functionality without disruption. However, a set of hanging states (a group of states not deeply embedded) has been observed and if any of these is deleted, the watermark could be removed and possibly the original IP Core functionality would not be disrupted, allowing for copyright infringements. Thus, a reduction procedure is applied to the watermarked design to reduce the number of hanging states, which to the best of the authors' knowledge has not been developed. Both FSM merging and reduction are NP-Complete problems. In this study, an improved objective function is proposed to accurately model the FSM reduction problem while applying GAs as optimization techniques at both stages. Empirical results show a significant improvement in terms of the number of final hanging states and watermark embedding strength as regards previous reported approaches.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116173486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Enabling partial reconfiguration for coprocessors in mixed criticality multicore systems using PCI express single-root I/O virtualization 使用PCI express单根I/O虚拟化为混合临界多核系统中的协处理器启用部分重新配置

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032516

Viet Vu Duy, O. Sander, T. Sandmann, S. Bähr, Jan Heidelberger, J. Becker

{"title":"Enabling partial reconfiguration for coprocessors in mixed criticality multicore systems using PCI express single-root I/O virtualization","authors":"Viet Vu Duy, O. Sander, T. Sandmann, S. Bähr, Jan Heidelberger, J. Becker","doi":"10.1109/ReConFig.2014.7032516","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032516","url":null,"abstract":"Especially in complex system-of-systems scenarios, where multiple high-performance or real-time processing functions need to co-exist and interact, reconfigurable devices together with virtualization techniques show considerable promise to increase efficiency, ease integration and maintain functional and non-functional properties of the individual functions. In this paper, we propose a concept that leverages the advantages of FPGA's partial reconfiguration in heterogeneous mixed criticality multicore systems. We describe the basic idea how to handle the partial reconfiguration transparently for non-critical tasks, while providing full control and a predictable behavior for safety relevant tasks. Our prototype is implemented on an Intel multicore system and a Xilinx Virtex-7 FPGA connected via PCI Express (PCIe), taking advantage of the Single-Root I/O Virtualization (SR-IOV) capabilities in modern PCIe implementations. Preliminary experimental results show that our concept achieves significantly shorter reconfiguration time with lower variance compared to other solutions.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116554927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Smart employment of circuit redundancy to effectively counter trojans (SECRET) in third-party IP cores 智能利用电路冗余，有效对抗第三方IP核中的木马(SECRET)

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032562

Mohammed M. Farag, M. Ewais

{"title":"Smart employment of circuit redundancy to effectively counter trojans (SECRET) in third-party IP cores","authors":"Mohammed M. Farag, M. Ewais","doi":"10.1109/ReConFig.2014.7032562","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032562","url":null,"abstract":"Hardware Trojan horses (HTHs) are malicious inclusions or alterations to hardware designs developed and supplied by untrusted parties. The emerging threat of HTHs has a direct impact on the FPGA design community which mainly relies on third-party IP (3PIP) cores and design reuse practices. Efficient design and detection of HTHs have been the main interest of most related research work, but countermeasures against HTHs have not attained sufficient attention. We advance a novel approach promoting Smart Employment of Circuit Redundancy to Effectively Counter Trojans (SECRET) in 3PIP cores employed in reconfigurable hardware designs. Two identical instances of the protected IP core are employed for observation and operating purposes and a time shift is created between the two core inputs. Trojan detection circuitry is inserted during the design-time to monitor the observation core at run-time. Once a Trojan is detected in the observation core, the operating core with the delayed input is suspended or the identified triggering inputs are isolated for a specific period of time to bypass the Trojan activating trigger. We present the SECRET high-level architecture, a proof-of-concept application to a 3PIP crypto core containing an HTH of our design. The prototype is designed and validated on a Spartan-3 FPGA. Simulation and implementation results show the SECRET feasibility and effectiveness.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124183404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

RAR-NoC: A reconfigurable and adaptive routable Network-on-Chip for FPGA-based multiprocessor systems 基于fpga的多处理器系统的可重构自适应路由片上网络

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032552

J. Rettkowski, D. Göhringer

引用次数: 18

A practical scheme for implementing dynamic spectral precoding in OFDM 一种在OFDM中实现动态频谱预编码的实用方案

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032550

E. Lizarraga, G. Corral-Briones

{"title":"A practical scheme for implementing dynamic spectral precoding in OFDM","authors":"E. Lizarraga, G. Corral-Briones","doi":"10.1109/ReConFig.2014.7032550","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032550","url":null,"abstract":"In wireless dynamic spectrum access (DSA) networks, orthogonal frequency-division multiplexing (OFDM) is an attractive modulation technique to enable coexistence of primary (legacy) and secondary users. In these systems, the use of cognitive radio (CR) promises to achieve high levels of efficiency in spectrum management. Focused on the operation of a secondary transmitter, emphasis is placed on the necessity of adapting the spectral shaping dynamically. To this end, we propose an architecture suitable for updating the spectral precoder according to changing wireless link conditions. In particular, in this paper we consider precoding techniques based on orthogonal projection of the information symbols. This specific precoding requires the generation of a constraint matrix that involves nonlinear operations, and the inversion of matrices with relatively large dimensions. Thus the overall processing remains challenging for FPGA implementations. A novel implementation scheme is proposed for fixed-point arithmetic which is appropriate when the constraint matrix satisfies certain conditions that ensures that involved variables can be adequately represented in this numerical system. Moreover, we identify the critical operations that firstly affect the stability of the updating processing and propose an hybrid architecture with fixed-point calculations and floating-point counterparts. The perspective in this stage is to deal with spectral shaping settings that may incur in an increased demand of stability. Finally, we analyze numerical conditions that require full floating-point calculations in order to achieve a numerically stable solution. A comparison between a floating-point computational model and the hybrid architecture implemented indicates high numerical robustness for the proposed approach.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130798027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An adaptive victim cache scheme 一种自适应受害者缓存方案

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032496

O. Navarro, M. Hübner

引用次数: 4