2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)最新文献_第2页

Improving reconfiguration speed for dynamic circuit specialization using placement constraints 利用放置约束提高动态电路专门化的重构速度

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032534

Amit Kulkarni, Tom Davidson, Karel Heyse, D. Stroobandt

{"title":"Improving reconfiguration speed for dynamic circuit specialization using placement constraints","authors":"Amit Kulkarni, Tom Davidson, Karel Heyse, D. Stroobandt","doi":"10.1109/ReConFig.2014.7032534","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032534","url":null,"abstract":"Dynamic Circuit Specialization (DCS) is an optimization technique used for implementing a parameterized application on an FPGA. The application is said to be parameterized when some of its inputs, called parameters, are infrequently changing compared to the other inputs. Instead of implementing these parameter inputs as regular inputs, in the DCS approach these inputs are implemented as constants and the design is optimized for these constants. When the parameter values change, the design is re-optimized for the new constant values by reconfiguring the FPGA. It has been investigated that run-time reconfiguration speed is the limiting factor of the DCS implementations on Xilinx FPGAs. We propose an idea to constrain the design's placement and use the custom Xilinx HWICAP driver to improve reconfiguration speed at the cost of a small reduction in design performance. We use Xilinx Virtex-5 and Zynq-SoC as experimental platforms and we have used an 8-bit FIR filter with different tap configurations as our parameterized design whose filter coefficient values are infrequently changing inputs. A drastic improvement in the reconfiguration speed with a factor of 14 is achieved with only a ≈ 6% decrease in performance.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122117121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

An AXI compatible cypress EZ-USB FX3 interface for USB-3.0 SuperSpeed AXI兼容的柏树EZ-USB FX3接口，用于USB-3.0 SuperSpeed

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032498

Benedikt Janßen, M. Hübner, T. Jaeschke

引用次数: 5

FPGA implementation of a reconfigurable image encryption system 一种可重构图像加密系统的FPGA实现

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032524

M. Ramírez-Torres, J. S. Ibarra, M. Mejía-Carlos

引用次数: 9

A hardware-assisted proof-of-concept for secure VoIP clients on untrusted operating systems 一个硬件辅助的概念验证，用于不受信任的操作系统上的安全VoIP客户端

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032489

Maik Ender, Gerd Duppmann, A. Wild, T. Pöppelmann, T. Güneysu

引用次数: 2

A highly flexible reconfigurable system on a Xilinx FPGA 基于赛灵思FPGA的高度灵活可重构系统

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032531

Tomas Drahonovsky, M. Rozkovec, O. Novák

引用次数: 4

On providing scalable self-healing adaptive fault-tolerance to RTR SoCs 为RTR soc提供可扩展的自修复自适应容错

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032541

Byron Navas, Johnny Öberg, I. Sander

{"title":"On providing scalable self-healing adaptive fault-tolerance to RTR SoCs","authors":"Byron Navas, Johnny Öberg, I. Sander","doi":"10.1109/ReConFig.2014.7032541","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032541","url":null,"abstract":"The dependability of heterogeneous many-core FPGA based systems are threatened by higher failure rates caused by disruptive scales of integration, increased design complexity, and radiation sensitivity. Triple-modular redundancy (TMR) and run-time reconfiguration (RTR) are traditional fault-tolerant (FT) techniques used to increase dependability. However, hardware redundancy is expensive and most approaches have poor scalability, flexibility, and programmability. Therefore, innovative solutions are needed to reduce the redundancy cost but still preserve acceptable levels of dependability. In this context, this paper presents the implementation of a self-healing adaptive fault-tolerant SoC that reuses RTR IP-cores in order to self-assemble different TMR schemes during run-time. The presented system demonstrates the feasibility of the Upset-Fault-Observer concept, which provides a run-time self-test and recovery strategy that delivers fault-tolerance over functions accelerated in RTR cores, at the same time reducing the redundancy scalability cost by running periodic reconfigurable TMR scan-cycles. In addition, this paper experimentally evaluates the trade-off of the implemented reconfigurable TMR schemes by characterizing important fault tolerant metrics i.e., recovery time (self-repair and self-replicate), detection latency, self-assembly latency, throughput reduction, and increase of physical resources.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115251242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Low power RAM-based hierarchical CAM on FPGA 基于FPGA的低功耗ram分层CAM

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032536

Z. Qian, M. Margala

{"title":"Low power RAM-based hierarchical CAM on FPGA","authors":"Z. Qian, M. Margala","doi":"10.1109/ReConFig.2014.7032536","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032536","url":null,"abstract":"Content Addressable Memories (CAMs) have been widely used to implement various high speed search functions in network devices such as routers and servers. In these devices, the role of CAM is to classify, drop or forward internet packets (i.e., packet classification). However, CAM suffers from several shortcomings such as high power consumption and low integration density. In addition, CAM is not available in most of modern Field Programmable Gate Array (FPGA), which has broad applications in network infrastructures. Therefore RAM-based CAM emulation has emerged as a promising alternative to CAM not only because RAM is a relatively mature technology but also due to the fact that there are more and larger RAM blocks on modern FPGA. In this paper, we propose a hierarchical search scheme for RAM-based CAM on FPGA. If a match is found in previous blocks, no subsequent search will be triggered and therefore average power consumption is reduced. Comparing with previous works which have not employed this technique, simulation results show that our method could reduce the power consumption up to 11.0% and 9.7% for block RAM based and distributed RAM based implementation respectively.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116177864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

The speed-up of detection of space debris using "InterP" and "FLOPS2D" 利用“InterP”和“FLOPS2D”加速空间碎片探测

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032556

N. Fujita, T. Yanagisawa, H. Kurosaki, H. Oda

引用次数: 0

On the performance and energy efficiency of FPGAs and GPUs for polyphase channelization 多相信道化fpga和gpu的性能和能效研究

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032542

Vignesh Adhinarayanan, Thaddeus Koehn, Krzysztof Kepa, Wu-chun Feng, P. Athanas

{"title":"On the performance and energy efficiency of FPGAs and GPUs for polyphase channelization","authors":"Vignesh Adhinarayanan, Thaddeus Koehn, Krzysztof Kepa, Wu-chun Feng, P. Athanas","doi":"10.1109/ReConFig.2014.7032542","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032542","url":null,"abstract":"Wideband channelization is an important and computationally demanding task in the front-end subsystem of several software-defined radios (SDRs). The hardware that supports this task should provide high performance, consume low power, and allow flexible implementations. Several classes of devices have been explored in the past, with the FPGA proving to be the most popular as it reasonably satisfies all three requirements. However, the growing presence of low-power mobile GPUs holds much promise with improved flexibility for instant adaptation to different standards. Thus, in this paper, we present optimized polyphase channelizations for the FPGA and GPU, respectively, that must consider power and accuracy requirements in the context of a military application. The performance in mega-samples per second (MSPS) and energy efficiency in MSPS/watt are compared between the two classes of hardware platforms: FPGA and GPU. The results show that by exploiting the flexible datapath width of FPGAs, FPGA implementations generally deliver an order-of-magnitude better performance and energy efficiency over fixed-width GPU architectures.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130403518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

PAMS: Pattern Aware Memory System for embedded systems 用于嵌入式系统的模式感知存储器系统

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032544

Tassadaq Hussain, Nehir Sönmez, Oscar Palomar, O. Unsal, A. Cristal, E. Ayguadé, M. Valero, Shakaib A. Gursal

引用次数: 3