PAMS: Pattern Aware Memory System for embedded systems

Abstract

In this paper, we propose a hardware mechanism for embedded multi-core memory system called Pattern Aware Memory System (PAMS). The PAMS supports static and dynamic data structures using descriptors and specialized memory and reduces area, cost, energy consumption and hit latency. When compared with a Baseline Memory System, the PAMS consumes between 3 and 9 times and 1.13 and 2.66 times less program memory for static and dynamic data structures respectively. The benchmarking applications (having static and dynamic data structures) results show that PAMS consumes 20% less hardware resources, 32% less on chip power and achieves a maximum speedup of 52× and 2.9× for static and dynamic data structures respectively. The results show that the PAMS multi-core system transfers data structures up to 4.65× faster than the MicroBlaze baseline system.