2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)最新文献_第3页

Tincr — A custom CAD tool framework for Vivado 为Vivado定制的CAD工具框架

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032560

Brad White, B. Nelson

引用次数: 22

Design of an attention detection system on the Zynq-7000 SoC 基于Zynq-7000 SoC的注意力检测系统设计

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032510

Fynn Schwiegelshohn, M. Hübner

{"title":"Design of an attention detection system on the Zynq-7000 SoC","authors":"Fynn Schwiegelshohn, M. Hübner","doi":"10.1109/ReConFig.2014.7032510","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032510","url":null,"abstract":"In this paper, we introduce a prototype attention detection system for automotive drivers. The driver is monitored through a Microsoft Kinect camera which provides RGB, depth, and infrared images in order to cover situations in which normal cameras might not achieve good results. The Kinect is connected to a Xilinx ZedBoard wich uses a Zynq-7000 SoC as processing platform. The attention detection system is running on the ARM Cortex-A9 dual core processor of the Zynq-7000 SoC. The system needs to recognize the drivers face and eyes in order to determine his state of attention. If the driver is classified as being attentive, no warning is generated. If the driver is classified as being inattentive, the system will generate a warning. Several algorithmic optimizations have been implemented in order to increase performance of this solution. In order to simulate a realistic driving environment, we have connected the Xilinx ZedBoard with a car simulator. This provides us with the necessary real world data to validate our system design. When our detection system classifies a driver as distracted or drowsy, it will send a warning message to the car simulator. The results show that the system performs satisfactorily when a face is detected. However, if no face is detected, the frame rate drops below an acceptable level.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124221362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Zero-latency datapath error correction framework for over-clocking DSP applications on FPGAs fpga上超频DSP应用的零延迟数据路径纠错框架

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032566

R. Duarte, C. Bouganis

引用次数: 3

Overloaded CDMA bus topology for MPSoC interconnect 用于MPSoC互连的过载CDMA总线拓扑

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032543

K. E. Ahmed, Mohammed M. Farag

{"title":"Overloaded CDMA bus topology for MPSoC interconnect","authors":"K. E. Ahmed, Mohammed M. Farag","doi":"10.1109/ReConFig.2014.7032543","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032543","url":null,"abstract":"Intra-chip communication is a major bottleneck in modern multiprocessor system-on-chip (MPSoC) designs. The bus topology is the most common on-chip interconnect technology and bus contention in one of the major issues in bus-based MPSoC designs. Code division multiple access (CDMA) has been proposed as a bus sharing strategy to overcome the bus contention problem. In CDMA, a limited number of orthogonal spreading codes can share the medium due to the Multiple Access Interference (MAI) problem. In wireless communications, overloaded CDMA has been considered to increase the system capacity by adding extra non-orthogonal spreading codes with specific characteristics. We propose a novel CDMA bus architecture leveraging the overloaded CDMA concepts to increase the maximum number of cores sharing the same CDMA bus in MPSoC by 25% at a marginal cost. The overloaded CDMA bus architecture is illustrated, resource- and speed-efficient decoding circuits are presented, and a prototype system is implemented and validated on a Virtex-7 FPGA VC707 evaluation kit. The overloaded and ordinary CDMA bus architectures are compared in terms of resource usage, power consumption, bus operating clock frequency and bandwidth. Evaluation results show an improvement in resource utilization and power consumption per unit (IP core) and the bus bandwidth by approximately %25 while preserving the access delay of the ordinary CDMA bus.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117277552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Side-channel power analysis of different protection schemes against fault attacks on AES AES故障攻击下不同保护方案的侧道功率分析

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032555

Pei Luo, Yunsi Fei, Liwei Zhang, A. Ding

引用次数: 18

Parameterised FPGA reconfigurations for efficient test set generation 参数化FPGA重构，高效生成测试集

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032545

Alexandra Kourfali, Elias Vansteenkiste, D. Stroobandt

引用次数: 1

High-throughput hash-based online traffic classification engines on FPGA 基于FPGA的高通量哈希在线流量分类引擎

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032530

Vaibhav R. Gandhi, Yun Qu, V. Prasanna

{"title":"High-throughput hash-based online traffic classification engines on FPGA","authors":"Vaibhav R. Gandhi, Yun Qu, V. Prasanna","doi":"10.1109/ReConFig.2014.7032530","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032530","url":null,"abstract":"Traffic classification is used to perform important network management tasks such as flow prioritization and traffic shaping/pricing. Machine learning techniques such as the C4.5 algorithm can be used to perform traffic classification with very high levels of accuracy; however, realizing high-performance online traffic classification engine is still challenging. In this paper, we propose a high-throughput architecture for online traffic classification on FPGA. We convert the C4.5 decision-tree into multiple hash tables. We construct a pipelined architecture consisting of multiple processing elements; each hash table is searched in a processing element independently. The throughput is further increased by using multiple pipelines in parallel. To evaluate the performance of our architecture, we implement it on a state-of-the-art FPGA. Post-place-and-route results show that, for a typical 128-leaf decision-tree used for online traffic classification, our classification engine sustains a throughput of 1654 Million Classifications Per Second (MCPS). Our architecture sustains high throughput even if the number of leaves in the decision-tree is scaled up to 1K. Compared to existing online traffic classification engines on various platforms, we achieve at least 3.5× speedup with respect to throughput.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116534131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

An architectural approach for reconfigurable industrial I/O devices 可重构工业I/O设备的体系结构方法

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032500

Daniel Kirschberger, Holger Flatt, J. Jasperneite

{"title":"An architectural approach for reconfigurable industrial I/O devices","authors":"Daniel Kirschberger, Holger Flatt, J. Jasperneite","doi":"10.1109/ReConFig.2014.7032500","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032500","url":null,"abstract":"This paper presents an architecture concept for reconfigurable industrial I/O devices. In order to avoid the use of special hardware modules as well as to offload the PLC from real-time preprocessing of sensor data, these tasks are shifted into the reconfigurable I/O device. Therefore, an FPGA based architecture template is proposed that supports loading of application-specific functions into the I/O device at runtime. The architecture template is partitioned into a static part and several reconfigurable slots. While the static part implements all fixed design elements, like the communication with the field bus and the in-system CPU, all application-specific functions are mapped onto the reconfigurable slots. In order to perform the reconfiguration of application-specific functions at runtime, the partial reconfiguration technology of modern FPGAs is used. The proposed concept is evaluated by mapping a case study with four reconfigurable slots onto a Xilinx Zynq-7000 SoC. The results show that new application-specific functions can be flexibly loaded into the I/O device. The total reconfiguration process of exemplary application-specific functions requires up to 3 ms and cause down-times below 0.5 ms. This especially enables new control applications that can even change the preprocessing within I/O devices during cyclic data communication.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120890959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Kernel-centric acceleration of high accuracy stereo-matching 高精度立体匹配的核中心加速度

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032535

Tobias Kenter, Henning Schmitz, Christian Plessl

{"title":"Kernel-centric acceleration of high accuracy stereo-matching","authors":"Tobias Kenter, Henning Schmitz, Christian Plessl","doi":"10.1109/ReConFig.2014.7032535","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032535","url":null,"abstract":"Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129593183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

What limits the operating frequency of a soft processor design 是什么限制了软处理器设计的工作频率

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032565

Kaveh Aasaraai, Andreas Moshovos

引用次数: 1