{"title":"An architectural approach for reconfigurable industrial I/O devices","authors":"Daniel Kirschberger, Holger Flatt, J. Jasperneite","doi":"10.1109/ReConFig.2014.7032500","DOIUrl":null,"url":null,"abstract":"This paper presents an architecture concept for reconfigurable industrial I/O devices. In order to avoid the use of special hardware modules as well as to offload the PLC from real-time preprocessing of sensor data, these tasks are shifted into the reconfigurable I/O device. Therefore, an FPGA based architecture template is proposed that supports loading of application-specific functions into the I/O device at runtime. The architecture template is partitioned into a static part and several reconfigurable slots. While the static part implements all fixed design elements, like the communication with the field bus and the in-system CPU, all application-specific functions are mapped onto the reconfigurable slots. In order to perform the reconfiguration of application-specific functions at runtime, the partial reconfiguration technology of modern FPGAs is used. The proposed concept is evaluated by mapping a case study with four reconfigurable slots onto a Xilinx Zynq-7000 SoC. The results show that new application-specific functions can be flexibly loaded into the I/O device. The total reconfiguration process of exemplary application-specific functions requires up to 3 ms and cause down-times below 0.5 ms. This especially enables new control applications that can even change the preprocessing within I/O devices during cyclic data communication.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ReConFig.2014.7032500","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper presents an architecture concept for reconfigurable industrial I/O devices. In order to avoid the use of special hardware modules as well as to offload the PLC from real-time preprocessing of sensor data, these tasks are shifted into the reconfigurable I/O device. Therefore, an FPGA based architecture template is proposed that supports loading of application-specific functions into the I/O device at runtime. The architecture template is partitioned into a static part and several reconfigurable slots. While the static part implements all fixed design elements, like the communication with the field bus and the in-system CPU, all application-specific functions are mapped onto the reconfigurable slots. In order to perform the reconfiguration of application-specific functions at runtime, the partial reconfiguration technology of modern FPGAs is used. The proposed concept is evaluated by mapping a case study with four reconfigurable slots onto a Xilinx Zynq-7000 SoC. The results show that new application-specific functions can be flexibly loaded into the I/O device. The total reconfiguration process of exemplary application-specific functions requires up to 3 ms and cause down-times below 0.5 ms. This especially enables new control applications that can even change the preprocessing within I/O devices during cyclic data communication.