What limits the operating frequency of a soft processor design

Abstract

This work systematically explores what limits the operation frequency in a typical general purpose, soft processor design on a modern FPGA. The analysis mirrors a typical design cycle: It starts from a base implementation of a 5-stage pipelined core where correctness, modularity, and speed of development are the primary considerations. The analysis then proceeds in a series of identify-and-then-revise steps. At each step, the analysis identifies the critical path and then "removes " it. The result is a list of components and mechanisms that restrict the frequency of operation. A designer would have to cleverly redesign over these paths in order to improve the processor's operating clock frequency. Using the results of this analysis, this work proposes various optimizations to improve the efficiency of some of these components. The optimizations increase the processor clock frequency from 145MHz to 281MHz on Stratix III devices, while overall instruction processing throughput increases by 80%.