RAR-NoC: A reconfigurable and adaptive routable Network-on-Chip for FPGA-based multiprocessor systems

Abstract

This paper presents a reconfigurable and adaptive routable Network-on-Chip (NoC) called RAR-NoC, which can be adapted at runtime to the application requirements. Therefore, RAR-NoC supports runtime reconfiguration of the routers as well as dynamic selection of the routing algorithm (XY or West-First) for each message. To evaluate the benefits of this flexible architecture, a heterogeneous reconfigurable multiprocessor system consisting of the ARM dual-core processor and several MicroBlaze processors has been developed and implemented on a Xilinx Zynq device. Network interfaces have been designed to efficiently connect the different processors to RAR-NoC. To analyze the data throughput and the channel utilization of the NoC at runtime, a centralized monitor core was developed and integrated. The required resources have been measured and it can be seen, that the area overhead for supporting both routing algorithms is less than 11%. Finally, it has been shown that RAR-NoC can avoid hotspots and therefore provides a higher throughput.