Adaptive and reconfigurable fault-tolerant routing method for 2D Networks-on-Chip

Abstract

Networks-on-Chip (NoCs) are becoming more susceptible to faults due to the increasing density in the VLSI circuits. As a result, designing reliable and efficient routing methods is highly desirable. Most of the existing fault-tolerant routing techniques use nonminimal paths to reroute the packets around the faulty regions. Using these approaches, the network performance degrades drastically not only by taking unnecessary longer paths, but also by creating hotspots around the faults. Moreover, they are designed statically and cannot adapt to the dynamic traffic distribution in the network. In this paper, a reconfigurable and fault-tolerant routing method is proposed which is designed based on the Abacus Turn Model (AbTM). The presented deadlock-free routing technique is dynamically tuned based on the location of faults and congestion in the network. Thus, it is able to tolerate all single router failures without exploiting virtual channels. Moreover, it can grant full adaptiveness to the hotspot regions of the network. Using this scheme, the rerouting is minimized by forwarding the packets through the available shortest paths. This efficiency makes the proposed method a powerful asset for reliable routing in NoCs.