{"title":"用于ASIC调试和快速系统原型的硬件/软件基础设施","authors":"Peter Reichel, Jens Döge","doi":"10.1109/ReConFig.2014.7032532","DOIUrl":null,"url":null,"abstract":"FPGAs are a key enabling technology for rapid and efficient system prototyping and initial commissioning of newly developed integrated circuits. One major aspect is the setup and control of interface components between devices under test (DUT) and the FPGA infrastructure. So, as to maintain high flexibility in conjunction with the ability to deal with changes of requirements and use cases, as well as unforeseen or faulty behavior of the DUT, we propose a novel reconfigurable hardware/software infrastructure. IP blocks, such as register files or interface components to external hardware are attached as leafs to a tree-like communication system optimized for alterations. It is designed as an Embedded Linux compatible CPU subsystem to be accessed from user space via a uniform and portable kernel driver. Thus, it implements transparent access to custom functionality from user applications without specific knowledge concerning the hardware/software coupling.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Hardware/software infrastructure for ASIC commissioning and rapid system prototyping\",\"authors\":\"Peter Reichel, Jens Döge\",\"doi\":\"10.1109/ReConFig.2014.7032532\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"FPGAs are a key enabling technology for rapid and efficient system prototyping and initial commissioning of newly developed integrated circuits. One major aspect is the setup and control of interface components between devices under test (DUT) and the FPGA infrastructure. So, as to maintain high flexibility in conjunction with the ability to deal with changes of requirements and use cases, as well as unforeseen or faulty behavior of the DUT, we propose a novel reconfigurable hardware/software infrastructure. IP blocks, such as register files or interface components to external hardware are attached as leafs to a tree-like communication system optimized for alterations. It is designed as an Embedded Linux compatible CPU subsystem to be accessed from user space via a uniform and portable kernel driver. Thus, it implements transparent access to custom functionality from user applications without specific knowledge concerning the hardware/software coupling.\",\"PeriodicalId\":137331,\"journal\":{\"name\":\"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ReConFig.2014.7032532\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ReConFig.2014.7032532","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Hardware/software infrastructure for ASIC commissioning and rapid system prototyping
FPGAs are a key enabling technology for rapid and efficient system prototyping and initial commissioning of newly developed integrated circuits. One major aspect is the setup and control of interface components between devices under test (DUT) and the FPGA infrastructure. So, as to maintain high flexibility in conjunction with the ability to deal with changes of requirements and use cases, as well as unforeseen or faulty behavior of the DUT, we propose a novel reconfigurable hardware/software infrastructure. IP blocks, such as register files or interface components to external hardware are attached as leafs to a tree-like communication system optimized for alterations. It is designed as an Embedded Linux compatible CPU subsystem to be accessed from user space via a uniform and portable kernel driver. Thus, it implements transparent access to custom functionality from user applications without specific knowledge concerning the hardware/software coupling.