D. Roggen, Stephane Hofmann, Y. Thoma, D. Floreano
{"title":"Hardware spiking neural network with run-time reconfigurable connectivity in an autonomous robot","authors":"D. Roggen, Stephane Hofmann, Y. Thoma, D. Floreano","doi":"10.1109/EH.2003.1217666","DOIUrl":"https://doi.org/10.1109/EH.2003.1217666","url":null,"abstract":"A cellular hardware implementation of a spiking neural network with run-time reconfigurable connectivity is presented. It is implemented on a compact custom FPGA board, which provides a powerful reconfigurable hardware platform for hardware and software design. Complementing the system, a CPU synthesized on the FPGA takes care of interfacing the network with the external world. The FPGA board and the hardware network are demonstrated in the form of a controller embedded on the Khepera robot for a task of obstacle avoidance. Finally, future implementations on new multi-cellular hardware are discussed.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131549237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Easily testable image operators: the class of circuits where evolution beats engineers","authors":"L. Sekanina, R. Ruzicka","doi":"10.1109/EH.2003.1217658","DOIUrl":"https://doi.org/10.1109/EH.2003.1217658","url":null,"abstract":"The paper deals with a class of image filters in which the evolutionary approach consistently produces excellent and innovative results. Furthermore, a method is proposed that leads to the automatic design of easily testable circuits. In particular we evolved \"salt and pepper\" noise filters, random shot noise filters, Gaussian noise filters, uniform random noise filters, and edge detectors.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121236957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementing evolution of FIR-filters efficiently in an FPGA","authors":"Knut Arne Vinger, J. Tørresen","doi":"10.1109/EH.2003.1217639","DOIUrl":"https://doi.org/10.1109/EH.2003.1217639","url":null,"abstract":"Reconfigurable hardware devices make it possible to change the topology of electronic circuits at runtime. Using reconfigurable devices as a platform for evolvable hardware (EHW) is well suited for real-time adaptive systems. This paper contains a novel approach on how to evolve the parameters for an adaptive digital filter. Both the filter as well as the evolution is implemented in a single field programmable gate array (FPGA). The circuit is based on context-switching in FPGA-devices and preliminary results indicate a compact hardware as well as fast adaptation.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123330686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jorge Luís Machado do Amaral, Jose F. M. Amaral, C. C. Santini, R. Tanscheit, M. Vellasco, M. Pacheco, A. C. M. Filho
{"title":"Evolvable building blocks for analog fuzzy logic controllers","authors":"Jorge Luís Machado do Amaral, Jose F. M. Amaral, C. C. Santini, R. Tanscheit, M. Vellasco, M. Pacheco, A. C. M. Filho","doi":"10.1109/EH.2003.1217652","DOIUrl":"https://doi.org/10.1109/EH.2003.1217652","url":null,"abstract":"This work discusses the use of an evolvable hardware (EHW) platform in the synthesis of analog electronic circuits for fuzzy logic controllers. A fuzzy logic controller (FLC) is defined by a collection of fuzzy if-then rules and a set of membership functions characterizing the linguistic terms associated with the inputs and output of the FLC. The EHW analog platform, named PAMA-NG (programmable analog multiplexer array - next generation), is a reconfigurable platform that consists of integrated circuits whose internal connections can be programmed by evolutionary computation techniques, such as genetic algorithms, to synthesize circuits. The PAMA-NG is classified as a field programmable analog array (FPAA). FPAAs have appeared recently and constitute the state of the art in the technology of reconfigurable platforms. These devices will become the building blocks of a forthcoming class of hardware, with the important features of self-adaptation and self-repairing, through automatic reconfiguration. This article focuses on the development of building blocks for analog FLCs on the PAMA-NG and presents case studies.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130369273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An embryonic array with improved efficiency and fault tolerance","authors":"R. Canham, A. Tyrrell","doi":"10.1109/EH.2003.1217678","DOIUrl":"https://doi.org/10.1109/EH.2003.1217678","url":null,"abstract":"Embryonic arrays are cellular based digital systems that make use of reconfigurable technologies to generate some features found in the embryonic development of biological entities. Typically a rectangular array of cells is implemented, each cell containing the complete description of the whole system. A coordinate system is used to select the functionality of each cell. This generates a quick method for reconfiguration, either to change functionality or to accommodate faults. This paper provides a brief review and critique of previous implementations before presenting a novel system. Unlike previous examples the array proposed only stores enough configuration data to accommodate a single fault or update. However, once this has occurred the system can reconfigure itself to be prepared for further faults or changes; this occurs in the background while the array still functions. The desired features of the array are provided but in a much more efficient manner. It also allows for a more fault tolerant implementation than current embryonic arrays.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127871116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
João P. B. Botelho, L. B. D. Sá, Pedro F. Vieira, A. C. M. Filho
{"title":"An experiment on nonlinear synthesis using evolutionary techniques based only on CMOS transistors","authors":"João P. B. Botelho, L. B. D. Sá, Pedro F. Vieira, A. C. M. Filho","doi":"10.1109/EH.2003.1217644","DOIUrl":"https://doi.org/10.1109/EH.2003.1217644","url":null,"abstract":"An experiment to perform analog circuits synthesis, using evolutionary techniques applied to circuits containing only integrated MOS transistors, is discussed. MOS transistors can operate as capacitors, resistors, switches and bipolar transistors. In an intrinsic evolutionary context, this simplifies considerably the design of field programmable analog arrays. The limitations of the approach are discussed in the paper.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124711538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Robot error detection using an artificial immune system","authors":"R. Canham, Alexander H. Jackson, A. Tyrrell","doi":"10.1109/EH.2003.1217667","DOIUrl":"https://doi.org/10.1109/EH.2003.1217667","url":null,"abstract":"Biology has produced living creatures that exhibit remarkable fault tolerance. The immune system is one feature that enables this. The acquired immune system learns during the life of the individual to differentiate between self (that which is normally present) and non-self (that which is not normally present). This paper describes an artificial immune system (AIS) that is used as an error detection system and is applied to two different robot based applications; the immunization of a fuzzy controller for a Khepera robot that provides object avoidance and a control module of a BAE Systems RASCAL/sup TM/ robot. The AIS learns normal behavior (unsupervised) during a fault free learning period and then identifies all error greater that a preset error sensitivity. The AIS was implemented in software but has the potential to be implemented in hardware. The AIS can be independent to the system under test, just requiring the inputs and outputs. This is not only ideal in terms of common mode and design errors but also offers the potential of a general, off-the-shelf, error detection system; the same AIS was applied to both the applications.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117297250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shotaro Kamio, Hongwei Liu, Hideyuki Mitsuhasi, H. Iba
{"title":"Researches on ingeniously behaving agents","authors":"Shotaro Kamio, Hongwei Liu, Hideyuki Mitsuhasi, H. Iba","doi":"10.1109/EH.2003.1217668","DOIUrl":"https://doi.org/10.1109/EH.2003.1217668","url":null,"abstract":"We have been studying the techniques for evolutionary robotics and experimenting with various robots applied evolutionary methods. We have paid special attentions to real robots and multi-agent problems related to them. In this research domain, we name them as \"ingeniously behaving agents\" (IBA). This paper shows several techniques developed in our IBA laboratory and their experimental results applied to simulations and real robots.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"1931 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128814300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An empirical comparison of evolutionary algorithms for evolvable with minimum time-to-reconfigure requirements","authors":"G. Greenwood, E. Ramsden, S. Ahmed","doi":"10.1109/EH.2003.1217646","DOIUrl":"https://doi.org/10.1109/EH.2003.1217646","url":null,"abstract":"Reconfigurability allows systems to adapt to changing operational environments. However, the time it takes to reconfigure cannot be ignored. Indeed, some critical systems must finish any reconfiguration within tight timeframes. This raises an important question: can an evolutionary algorithm designed to quickly search for the best initial configuration also be able to quickly search for a good reconfiguration? This paper reports the results of a study designed to identify those evolutionary algorithm features that help minimize the search time for reconfigurations of previously configured hardware. An active, analog filter reconfiguration problem is used as a test case.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123950969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Towards evolvable IP cores for FPGAs","authors":"L. Sekanina","doi":"10.1109/EH.2003.1217659","DOIUrl":"https://doi.org/10.1109/EH.2003.1217659","url":null,"abstract":"The paper deals with a new approach to the design of adaptive hardware using common field programmable gate arrays (FPGA). The ultimate aim is to develop evolvable IP (intellectual property) cores. The cores should be reused in the same way as ordinary IP cores are reused. In contrast to the conventional cores, the evolvable cores are able to perform autonomous evolution of their internal circuits. The cores should be available in the form of HDL source code, i.e. they should be synthesizable into any reconfigurable device of a sufficient capacity. The approach is based on implementation of a virtual reconfigurable circuit and a genetic unit in an ordinary FPGA. In the presented case study an adaptive image filter is designed, implemented and synthesized. The proposed idea of evolvable IP core could open the way towards defining a business model for evolvable hardware.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124153597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}