{"title":"Intrinsic hardware evolution for the design and reconfiguration of analog speed controllers for a DC Motor","authors":"D. Gwaltney, M. I. Ferguson","doi":"10.1109/EH.2003.1217650","DOIUrl":"https://doi.org/10.1109/EH.2003.1217650","url":null,"abstract":"Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a second generation field programmable transistor array (FPTA2). The performance of an evolved controller is compared to that of a conventional proportional-integral (PI) controller. It is shown that hardware evolution is able to create a compact design that provides good performance, while using considerably less functional electronic components than the conventional design. Additionally, the use of hardware evolution to provide fault tolerance by reconfiguring the design is explored. Experimental results are presented showing that significant recovery of capability can be made in the face of damaging induced faults.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132169469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. C. Coello, E. Alba, Gabriel Luque, A. H. Aguirre
{"title":"Comparing different serial and parallel heuristics to design combinational logic circuits","authors":"C. C. Coello, E. Alba, Gabriel Luque, A. H. Aguirre","doi":"10.1109/EH.2003.1217635","DOIUrl":"https://doi.org/10.1109/EH.2003.1217635","url":null,"abstract":"In this paper, we perform a comparative study of different heuristics used to design combinational logic circuits. The use of local search hybridized with a genetic algorithm and the effect of parallelism are of particular interest in the study conducted. Our results indicate that a hybridization of a genetic algorithm with simulated annealing is beneficial and that the use of parallelism does not only introduce a speedup (as expected) in the algorithms, but also allows one to improve the quality of the solutions found.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124822998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Tempesti, D. Mange, Enrico Petraglio, A. Stauffer, Y. Thoma
{"title":"Developmental processes in silicon: an engineering perspective","authors":"G. Tempesti, D. Mange, Enrico Petraglio, A. Stauffer, Y. Thoma","doi":"10.1109/EH.2003.1217677","DOIUrl":"https://doi.org/10.1109/EH.2003.1217677","url":null,"abstract":"In this article, we analyze the requirements of developmental processes from the perspective of their implementation in digital hardware. After recalling the motivations for such an implementation, we concentrate separately on the two mechanisms (cellular division and cellular differentiation) that are exploited by biological systems to realize development. We then describe some of the current and projected solutions to implement such mechanisms in hardware, and conclude by analyzing the most interesting features of developmental approaches.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134319539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automatic multi-module neural network evolution in an artificial brain","authors":"J. Dinerstein, N. Dinerstein, H. D. Garis","doi":"10.1109/EH.2003.1217679","DOIUrl":"https://doi.org/10.1109/EH.2003.1217679","url":null,"abstract":"A major problem in artificial brain building is the automatic construction and training of multi-module systems of neural networks. For example, consider a biological human brain, which has millions of neural nets. If an artificial brain is to have similar complexity, it is unrealistic to require that the training data set for each neural net must be specified explicitly by a human, or that interconnections between evolved nets be performed manually. In this paper we present an original technique to solve this problem. A single large-scale task (too complex to be performed by a single neural net) is automatically split into simpler sub-tasks. A multi-module system of neural nets is then trained so that one of these sub-tasks is performed by each net. We present the results of an experiment using this novel technique for pattern recognition.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132616217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Power dissipation reductions with genetic algorithms","authors":"E. Takahashi, M. Murakawa, Y. Kasai, T. Higuchi","doi":"10.1109/EH.2003.1217654","DOIUrl":"https://doi.org/10.1109/EH.2003.1217654","url":null,"abstract":"Two cases of power dissipation reduction with post-fabrication adjustment using genetic algorithms is introduced in this paper. The first is a 1GHz ALU implementation, where power consumption has been reduced by 54% through clock-timing adjustment. The second case is the IF (intermediate frequency) filter analog LSI used in cellular phones, where the reduction in power dissipation is realized by circuit parameter adjustment. The IF filter has been widely used in commercial cellular phones since 2001.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127143335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Lohn, D. Linden, G. Hornby, W. Kraus, A. Rodriguez-Arroyo
{"title":"Evolutionary design of an X-band antenna for NASA's Space Technology 5 mission","authors":"J. Lohn, D. Linden, G. Hornby, W. Kraus, A. Rodriguez-Arroyo","doi":"10.1109/EH.2003.1217660","DOIUrl":"https://doi.org/10.1109/EH.2003.1217660","url":null,"abstract":"We present an evolved X-band antenna design and flight prototype currently on schedule to be deployed on NASA's Space Technology 5 spacecraft in late 2004. The antenna was evolved to meet a challenging set of mission requirements, most notably the combination of wide beamwidth for a circularly polarized wave and wide bandwidth. The highest performance antenna found using a genetic algorithm was fabricated and tested.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117106120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Exploring FPGA structures for evolving fault tolerant hardware","authors":"A. P. Shanthi, R. Parthasarathi","doi":"10.1109/EH.2003.1217664","DOIUrl":"https://doi.org/10.1109/EH.2003.1217664","url":null,"abstract":"This work explores different types of FPGA (field programmable gate array) structures for evolving fault tolerant hardware. A three-tier model for providing fault tolerance to the digital circuits evolved on FPGAs is proposed. This model combines the process level redundancy provided by the GA (genetic algorithm) based evolution techniques and the structural level redundancy supported by the FPGA architectures. Simulation results using the ISCAS'89 benchmark circuits have been carried out to study the effect of granularity on the time taken for the evolution process, the dimensionality of the evolution and the number of solutions that need to be evolved for fault coverage. The effect of using a divide and conquer approach to reduce the time taken for evolution has been studied proving that this is a feasible approach even for complex circuits.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131259850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Data and signals: a new kind of cellular automaton for growing systems","authors":"A. Stauffer, M. Sipper","doi":"10.1109/EH.2003.1217672","DOIUrl":"https://doi.org/10.1109/EH.2003.1217672","url":null,"abstract":"Traditionally the cell of an automaton implements the rule table defining the state of the cell at the next time step knowing its present state and those of its neighbors. The cell consequently processes only with states. The novel cell presented here handles data and signals. It is designed as a digital system made up of a processing unit and a control unit. The realization of interactive self-replicating loops will serve as an application example of growing systems. The hardware implementation of these loops takes place in our electronic wall for bio-inspired applications, the BioWall.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127970347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Zebulum, D. Keymeulen, V. Duong, Xin Guo, M. I. Ferguson, A. Stoica
{"title":"Experimental results in evolutionary fault-recovery for field programmable analog devices","authors":"R. Zebulum, D. Keymeulen, V. Duong, Xin Guo, M. I. Ferguson, A. Stoica","doi":"10.1109/EH.2003.1217665","DOIUrl":"https://doi.org/10.1109/EH.2003.1217665","url":null,"abstract":"This paper presents experimental results of fast intrinsic evolutionary design and evolutionary fault recovery of a 4-bit digital to analog converter (DAC) using the JPL stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems and provides autonomous, fast (tens to hundreds of seconds), on-chip evolution involving about 100,000 circuit evaluations. Its main components are a JPL field programmable transistor array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper describes an experiment consisting of the hierarchical evolution of a 4-bit DAC using 20 cells of the FPTA chip. Fault-recovery is demonstrated after applying stuck-at 0 faults to all switches of one particular cell, and using evolution to recover functionality. It is verified that the functionality can be recovered in less than one minute after the fault is detected while the evolutionary design of the 4-bit DAC from scratch took about 3 minutes.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"24 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133391460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evolution of combinatorial and sequential online self-diagnosing hardware","authors":"Miguel Garvie, A. Thompson","doi":"10.1109/EH.2003.1217663","DOIUrl":"https://doi.org/10.1109/EH.2003.1217663","url":null,"abstract":"The evolution of circuits with online built-in self-test is attempted in simulation for a full adder, two-bit multiplier and edge triggered D-latch. Results show that the evolved designs perform full diagnosis using less or equal number of components than hand-designed equivalents.","PeriodicalId":134823,"journal":{"name":"NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121582609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}