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2009 IEEE International Symposium on Industrial Embedded Systems最新文献

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FPGA based soft sensor for the estimation of the kerosene freezing point 基于FPGA的煤油凝固点软测量
2009 IEEE International Symposium on Industrial Embedded Systems Pub Date : 2009-07-08 DOI: 10.1109/SIES.2009.5196219
R. Caponetto, G. Dongola, A. Gallo, M. Xibilia
{"title":"FPGA based soft sensor for the estimation of the kerosene freezing point","authors":"R. Caponetto, G. Dongola, A. Gallo, M. Xibilia","doi":"10.1109/SIES.2009.5196219","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196219","url":null,"abstract":"A new strategy to realize an FPGA implementation of a soft sensor for an industrial process is proposed. In order to cope with the problem of small data sets in the identification of a non linear model the proposed approach is based on the integration of bootstrap re-sampling, noise injection and stacked neural networks (NNs), using the Principal Component Analysis (PCA). The aggregated final NN-PCA system has been implemented on Field Programmable Gate Array (FPGA). The proposed method has been applied to develop a soft sensor for the estimation of the freezing point of kerosene in an atmospheric distillation unit (topping) working in a refinery in Sicily, Italy.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129214262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Minimizing expected energy consumption for streaming applications with linear dependencies on chip multiprocessors 最大限度地减少对芯片多处理器线性依赖的流应用程序的预期能耗
2009 IEEE International Symposium on Industrial Embedded Systems Pub Date : 2009-07-08 DOI: 10.1109/SIES.2009.5196201
Ahmed Abousamra, R. Melhem, D. Mossé
{"title":"Minimizing expected energy consumption for streaming applications with linear dependencies on chip multiprocessors","authors":"Ahmed Abousamra, R. Melhem, D. Mossé","doi":"10.1109/SIES.2009.5196201","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196201","url":null,"abstract":"Dynamic voltage scaling (DVS) is a widely applied power management mechanism in real-time systems. We propose an algorithm for scheduling periodic hard real-time streaming applications with linear dependencies and known probability distributions of computational requirements on chip multiprocessors (CMP). The goal of the scheduling is to minimize the expected energy consumption while satisfying two quality of service (QoS) requirements: throughput and response time. Our experiments show significant energy savings (up to 55%) over scheduling when only the worst case computational requirements are known. In addition, while dynamically reclaiming processor idle time across multiple processors yields small benefit when scheduling is based on the probability distribution of computational requirements, it results in significant energy savings when scheduling for the worst case, especially for applications with short deadlines.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116699153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Deadlock risk assessment in architectural models of real-time systems 实时系统体系结构模型中的死锁风险评估
2009 IEEE International Symposium on Industrial Embedded Systems Pub Date : 2009-07-08 DOI: 10.1109/SIES.2009.5196214
Antonio Monzón, José L. Fernández-Sánchez
{"title":"Deadlock risk assessment in architectural models of real-time systems","authors":"Antonio Monzón, José L. Fernández-Sánchez","doi":"10.1109/SIES.2009.5196214","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196214","url":null,"abstract":"Software Architectural Assessment is a key discipline to identify at early stages of a system synthesis the problems that may become critical in its operation. This matter is especially relevant for those systems with real-time constraints. In this paper a special emphasis shall be made on concurrency issues. Typical mechanisms supporting concurrency, such as semaphores or monitors, usually lead to concurrency problems in execution time hard to identify, reproduce and solve. For this reason it is crucial to understand the root causes of these problems and to provide support to identify and mitigate them at early stages of the system lifecycle.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134280783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Temporal data matching in component based real time systems 基于组件的实时系统中的时间数据匹配
2009 IEEE International Symposium on Industrial Embedded Systems Pub Date : 2009-07-08 DOI: 10.1109/SIES.2009.5196195
Nadège Pontisso, P. Quéinnec, G. Padiou
{"title":"Temporal data matching in component based real time systems","authors":"Nadège Pontisso, P. Quéinnec, G. Padiou","doi":"10.1109/SIES.2009.5196195","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196195","url":null,"abstract":"We consider embedded systems structured as a graph of communicating components [1]. In this model, we define a data matching property based upon the interactions of the data flow paths passing through common components. If a component uses inputs which indirectly depend on the same component output, these inputs have to depend on a same execution step of the producer component, even when several independent paths link these two components, and when the components have different timing characteristics (esp. different periods). We analyze the system architecture to detect situations that can cause data matching problems. Depending on the system needs, we propose several approaches to manage data matching.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128002300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Programmable temporal isolation through variable-bandwidth servers 可编程的时间隔离通过可变带宽的服务器
2009 IEEE International Symposium on Industrial Embedded Systems Pub Date : 2009-07-08 DOI: 10.1109/SIES.2009.5196213
Silviu S. Craciunas, C. Kirsch, H. Payer, Harald Röck, A. Sokolova
{"title":"Programmable temporal isolation through variable-bandwidth servers","authors":"Silviu S. Craciunas, C. Kirsch, H. Payer, Harald Röck, A. Sokolova","doi":"10.1109/SIES.2009.5196213","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196213","url":null,"abstract":"We introduce variable-bandwidth servers (VBS) for scheduling and executing processes under programmable temporal isolation. A VBS is an extension of a constant-bandwidth server where throughput and latency of process execution can not only be controlled to remain constant across different competing workloads but also to vary in time as long as the resulting bandwidth stays below a given bandwidth cap. We have designed and implemented a VBS-based EDF-style constant-time scheduling algorithm, a constant-time admission test, and four alternative queue management plugins which influence the scheduling algorithm's overall temporal and spatial complexity. Experiments confirm the theoretical bounds in a number of microbenchmarks and demonstrate that the scheduler can effectively manage in constant time any number of processes up to available memory while maintaining response times of individual processes within a bounded range. We have also developed a small-footprint, bare-metal virtual machine that uses VBS for temporal isolation of multiple, concurrently running processes executing real code.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128825851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
On link harness optimization of embedded Ethernet networks 嵌入式以太网链路线束优化研究
2009 IEEE International Symposium on Industrial Embedded Systems Pub Date : 2009-07-08 DOI: 10.1109/SIES.2009.5196215
J. Sommer, E. Doumith, Quentin Duval
{"title":"On link harness optimization of embedded Ethernet networks","authors":"J. Sommer, E. Doumith, Quentin Duval","doi":"10.1109/SIES.2009.5196215","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196215","url":null,"abstract":"During the last decades, Ethernet progressively became the most widely used Local Area Network (LAN) technology. It evolved from a bus topology to a micro-segmented network with full duplex links. Apart from LAN installations, Ethernet became also attractive for embedded application areas such as industrial, automotive, and avionics. In these areas, the connectivity between the nodes and the switches results in link harnesses. These harnesses can be bundled together and installed inside ducts. Since not all the links have the same endpoints, some full duplex links leave a duct at points referred to as junction points. In this paper, we propose a Simulated Annealing based algorithm to optimize the topology design of embedded Ethernet networks. This algorithm finds the (near-)optimal positions of a given number of switches and their connections to given nodes. When we take into account that links are organized into link harnesses and installed into ducts, we have to find also the number of junction points required as well as their optimal positions. For this purpose, we propose two algorithms. Finally, we compare the algorithms in terms of computation time and the quality of the obtained solution, and we highlight the cost benefits of bundling links and installing them into ducts.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130327486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Exploration of a digital audio processing platform using a compositional system level performance estimation framework 探索使用合成系统级性能评估框架的数字音频处理平台
2009 IEEE International Symposium on Industrial Embedded Systems Pub Date : 2009-07-08 DOI: 10.1109/SIES.2009.5196193
Anders Sejer Tranberg-Hansen, J. Madsen
{"title":"Exploration of a digital audio processing platform using a compositional system level performance estimation framework","authors":"Anders Sejer Tranberg-Hansen, J. Madsen","doi":"10.1109/SIES.2009.5196193","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196193","url":null,"abstract":"This paper presents the application of a compositional simulation based system-level performance estimation framework [1], [2] on a non-trivial industrial case study. The case study is provided by the Danish company Bang & Olufsen ICEpower a/s and focuses on the exploration of a digital mobile audio processing platform. A short overview of the compositional performance estimation framework used is given followed by a presentation of how it is used for performance estimation using an iterative refinement process towards the final implementation. Finally, an evaluation in terms of accuracy and speed of simulations is discussed based on the presented design flow applied to the case study in question.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"228 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134016194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The utilization bound of non-preemptive rate-monotonic scheduling in Controller Area Networks is 25% 控制器局域网中非抢占率单调调度的利用界为25%
2009 IEEE International Symposium on Industrial Embedded Systems Pub Date : 2009-07-08 DOI: 10.1109/SIES.2009.5196186
Björn Andersson, E. Tovar
{"title":"The utilization bound of non-preemptive rate-monotonic scheduling in Controller Area Networks is 25%","authors":"Björn Andersson, E. Tovar","doi":"10.1109/SIES.2009.5196186","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196186","url":null,"abstract":"Consider a distributed computer system comprising many computer nodes, each interconnected with a Controller Area Network (CAN) bus. We prove that if priorities to message streams are assigned using rate-monotonic (RM) and if the requested capacity of the CAN bus does not exceed 25% then all deadlines are met.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116522905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Enhancing AUTOSAR methodology to a cotsbased development process via mapping to V-Model 通过映射到V-Model，将AUTOSAR方法增强为基于成本的开发过程
2009 IEEE International Symposium on Industrial Embedded Systems Pub Date : 2009-07-08 DOI: 10.1109/SIES.2009.5196192
Manish Kumar, Jonghun Yoo, Seongsoo Hong
{"title":"Enhancing AUTOSAR methodology to a cotsbased development process via mapping to V-Model","authors":"Manish Kumar, Jonghun Yoo, Seongsoo Hong","doi":"10.1109/SIES.2009.5196192","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196192","url":null,"abstract":"AUTOSAR, an open standard for automotive software, is currently being exploited by the automotive industry. Although the standard mainly focuses on software architecture, it also provides a development methodology. Unfortunately, the methodology in its current form is insufficient for industrial exploitation because it describes only an incomplete set of activities, work products and their dependencies. Specifically, (1) the activities to support COTS-based development are missing even though AUTOSAR encourages the use of COTS components; (2) it does not describe the roles and their responsibilities; and (3) it does not specify the mapping of activities onto a complete process model. In this paper, we propose a new software development process for AUTOSAR by extending the existing methodology. In doing so, we add activities to allow COTS component selection, evaluation and integration. Then, we define specific roles and assign responsibilities to those roles. Finally, we describe the overall timeline of various activities in detail by mapping the activities to the V-model. In order to present the process, we have used SPEM 2.0 notation, which is backward compatible with the AUTOSAR methodology and has improved expressiveness. We have composed the proposed process model using Eclipse Process Framework Composer which not only performs a sanity check of the model but also provides a way to publish it.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129332019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Dependency-aware stochastic analysis of chained execution times 链式执行时间的依赖感知随机分析
2009 IEEE International Symposium on Industrial Embedded Systems Pub Date : 2009-07-08 DOI: 10.1109/SIES.2009.5196197
M. Ivers, R. Ernst
{"title":"Dependency-aware stochastic analysis of chained execution times","authors":"M. Ivers, R. Ernst","doi":"10.1109/SIES.2009.5196197","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196197","url":null,"abstract":"For the design of complex embedded systems, early performance estimation based on models of subsystems is used to decide about key parameters. With stochatic component models coming from different suppliers, the system integrator has the responsiblity to derive a meaningful system performance characterization from different component models.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130350245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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