G. Fortino, A. Guerrieri, F. Bellifemine, Roberta Giannantonio
{"title":"SPINE2: developing BSN applications on heterogeneous sensor nodes","authors":"G. Fortino, A. Guerrieri, F. Bellifemine, Roberta Giannantonio","doi":"10.1109/SIES.2009.5196205","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196205","url":null,"abstract":"Body sensor networks (BSNs) have great potential to enable a broad variety of assisted living applications such as health and activity monitoring, and emergency detection. Although several effective application development frameworks already exist for BSNs based on specific sensor platforms (e.g. CodeBlue, SPINE, Titan), effective methods for the platform-independent development of BSN applications are still missing. Such methods would enable rapid development of multi-platform applications and fast application porting from one platform to another. In this paper, we present SPINE2, an evolution of SPINE, which aims at reaching a very high platform independency and raising the level of the used programming abstractions by providing a task-oriented programming model. Furthermore, SPINE2 is exemplified through a case study related to human activity monitoring.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127599730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fault isolation with intermediate checks of end-to-end checksums in the Time-Triggered System-on-Chip Architecture","authors":"H. Paulitsch, C. Paukovits, C. E. Salloum","doi":"10.1109/SIES.2009.5196200","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196200","url":null,"abstract":"This paper deploys end-to-end message checksums for error detection in the Time-Triggered System-on-Chip Architecture (TTSoCA). The end-to-end checksums are not only checked at the end, but also intermediately in the communication subsystem of the System-on-Chips (SoCs) concurrently with the message transmission in order to isolate faults: if a message transmission error occurs, the goal is to pinpoint whether the fault has originated in an IP core, in the communication subsystem, or in a gateway.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122427672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SoC-level risk assessment using FMEA approach in system design with SystemC","authors":"Yung-Yuan Chen, Chung-Hsien Hsu, K. Leu","doi":"10.1109/SIES.2009.5196199","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196199","url":null,"abstract":"As system-on-chip (SoC) becomes prevalent in the intelligent system applications, the reliability issue of SoC is getting more attention in the design industry due to the rapid increasing rate of radiation-induced soft errors while the SoC fabrication enters the very deep submicron technology. Therefore, the SoC dependability becomes a critical issue in safety-critical applications. Validating such systems is imperative to guarantee the dependability of the systems before they are being put to use. Moreover, it is beneficial to assess the SoC robustness in early design phase in order to significantly reduce the cost and time of re-design. To fill such needs, in this study, we propose a useful IP-based SoC-level risk model using failure mode and effects analysis (FMEA) method to assess the robustness of a SoC in SystemC transaction-level modeling (TLM) design level. The proposed risk model is able to facilitate the measure of the robustness and scales of failure-induced risks in a system, which can be used to identify the critical components and major failure modes for protection so as to effectively reduce the impact of failures to the system. A case study is used to demonstrate our risk model under CoWare Platform Architect environment. A system verification tool was created to assist us in measuring the robustness of the system, in locating the weaknesses of the system, and in understanding the effect of faults on system failure behavior during the SoC design phase. The contribution of this work is to promote the dependability verification to TLM abstraction level that can significantly enhance the simulation performance, and provide the comprehensive results to validate the system dependability in early design phase for safety-critical applications.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115804939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Generative programming with support for formal verification","authors":"M. Paska","doi":"10.1109/SIES.2009.5196194","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196194","url":null,"abstract":"This paper presents a novel approach to software development, mainly useful for embedded devices. Embedded software is described in a programming language with very high level of abstraction. Efficient production code is generated from this description; also code suitable for formal verification is generated. The paper investigates efficiency of both the verifiable and the production code.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124323469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Robustness investigation of the FlexRay system","authors":"K. Leu, C. Wey, Jwu-E Chen, Yung-Yuan Chen","doi":"10.1109/SIES.2009.5196210","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196210","url":null,"abstract":"FlexRay, as a communication protocol for automotive control systems, is developed to fulfill the increasing demand on the electronic control units for implementing systems with higher safety and more comfort. Fault-tolerant feature is especially highlighted in the FlexRay protocol such that it can be robust enough to apply for the safety-critical automotive applications. In this work-in-progress report, a verification strategy of the fault-tolerant mechanisms (FTMs) adopted in the FlexRay protocol is introduced. Our goal is to assess the effectiveness of FTMs to common interferences including EMI, SEU and crosstalk. We will also build up a simplified steer-by-wire system for observing its abnormal behaviors when the FTMs cannot overcome the interferences. All the investigations provide a transparent figure to the robustness of the FlexRay systems.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129694189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Stellwag, Alexander Ditter, Wolfgang Schröder-Preikschat
{"title":"A wait-free queue for multiple enqueuers and multiple dequeuers using local preferences and pragmatic extensions","authors":"P. Stellwag, Alexander Ditter, Wolfgang Schröder-Preikschat","doi":"10.1109/SIES.2009.5196220","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196220","url":null,"abstract":"Queues are one of the most commonly used data structures in applications and operating systems [1]. Up-and-coming multi-core processors force software developers to consider data structures in order to make them thread-safe. But, in real-time systems, e.g., robotic controls, parallelization is even more complicated as such systems must guarantee to meet their mostly hard deadlines. A considerable amount of research has been carried out on wait-free objects [2] to achieve this. Wait-freedom can guarantee that each potentially concurrent thread completes its operation within a bounded number of steps. But applicable wait-free queues, which supports multiple enqueue, dequeue and read operations, do not exist yet. Therefore, we present a statically allocated and statically linked queue, which supports arbitrary concurrent operations. Our approach is also applicable in other scenarios, where unsorted queues with statically allocated elements are used. Moreover, we introduce ‘local preferences’ to minimize contention. But, as the response times of our enqueue operation directly depends on the fill level, the response times of a nearly filled queue still remain an issue. Moreover, our approach is jitter-prone with a varying fill level. In this paper, we also address all of these issues with an approach using a helping queue. The results show that we can decrease the worst case execution time by approximately factor twenty. Additionally, we reduce the average response times of potentially concurrent enqueue operations in our queue. To the best of our knowledge, our wait-free queue is the best known and practical solution for an unsorted thread-safe queue for multiple enqueuers, multiple dequeuers and mulitple readers.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"224 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120896506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"RoboArch: A component-based tool proposal for developing hardware architecture for mobile robots","authors":"Vanderlei Bonato, E. Marques","doi":"10.1109/SIES.2009.5196221","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196221","url":null,"abstract":"This paper introduces a component-based tool proposal for developing hardware architecture for mobile robots at ESL (Electronic System-Level) based on reusable IP (Intellectual Property) cores. This tool, denominated RoboArch, provides a platform independent development environment where embedded systems are created in a visual environment from IP component libraries specified according to the IP-XACT XML (Extensible Markup Language) schema, where a component can be a softcore processor, a dedicated hardware module or a high level model described in a non-synthesizable code. The systems developed in this visual programming environment can be either simulated directly at ESL (Electronic System-Level) using external environments for stimulus generation and result monitoring or synthesized for a hardware description representation at RTL (Register Transfer Language), allowing its implementation on FPGA (Field-Programmable Gate Array).","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128226541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Seto, A. Giani, Victor Shia, Curtis Wang, Posu Yan, A. Yang, M. Jerrett, R. Bajcsy
{"title":"A wireless body sensor network for the prevention and management of asthma","authors":"E. Seto, A. Giani, Victor Shia, Curtis Wang, Posu Yan, A. Yang, M. Jerrett, R. Bajcsy","doi":"10.1109/SIES.2009.5196203","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196203","url":null,"abstract":"We present an application of an open source platform for wireless body sensor network called DexterNet to the problem of children's asthma. The architecture of the system consists of three layers. At the body sensor layer (BSL), the integrated monitoring of a child's activities, geographic location, and air pollution exposures occurs. At the personal network layer (PNL), a wireless mobile device worn by the child summarizes the sensed data, and provides information feedback. The mobile device communicates wirelessly over the Internet with the third global network layer (GNL), in which a web server provides the following four information services: a clinical module that supports the healthcare management of asthma cases, a personal health module that supports individual prevention of asthma attacks, a community module that supports participatory sensing, and a health research module that supports the collection of anonymous sensor data for research into the risk factors associated with asthma. We illustrate the potential for the system to serve as a comprehensive strategy to manage asthma cases and prevent asthma attacks.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"772 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123888475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A method of computation for worst-case delay analysis on SpaceWire networks","authors":"Thomas Ferrandiz, F. Frances, C. Fraboul","doi":"10.1109/SIES.2009.5196187","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196187","url":null,"abstract":"SpaceWire is a standard for on-board satellite networks chosen by the ESA as the basis for future data-handling architectures. However, network designers need tools to ensure that the network is able to deliver critical messages on time. Current research only seek to determine probabilistic results for end-to-end delays on Wormhole networks like SpaceWire. This does not provide sufficient guarantee for critical traffic. Thus, in this paper, we propose a method to compute an upper-bound on the worst-case end-to-end delay of a packet in a SpaceWire network.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117085767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evaluation of an Esterel-based hardware/software co-design flow","authors":"P. Roessler, M. Zauner","doi":"10.1109/SIES.2009.5196190","DOIUrl":"https://doi.org/10.1109/SIES.2009.5196190","url":null,"abstract":"This work describes the evaluation of a hardware/software co-design flow based on the synchronous language Esterel. The paper starts with a short introduction into Esterel and tackles available tools. The focus of this work is an examination of the design flow concerning the practical applicability, based on case studies and related work. Advantages and draw-backs of the design flow are discussed and compared to traditional hardware/software design flows.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130980909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}