{"title":"基于esterel的硬件/软件协同设计流程的评估","authors":"P. Roessler, M. Zauner","doi":"10.1109/SIES.2009.5196190","DOIUrl":null,"url":null,"abstract":"This work describes the evaluation of a hardware/software co-design flow based on the synchronous language Esterel. The paper starts with a short introduction into Esterel and tackles available tools. The focus of this work is an examination of the design flow concerning the practical applicability, based on case studies and related work. Advantages and draw-backs of the design flow are discussed and compared to traditional hardware/software design flows.","PeriodicalId":133325,"journal":{"name":"2009 IEEE International Symposium on Industrial Embedded Systems","volume":"68 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Evaluation of an Esterel-based hardware/software co-design flow\",\"authors\":\"P. Roessler, M. Zauner\",\"doi\":\"10.1109/SIES.2009.5196190\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work describes the evaluation of a hardware/software co-design flow based on the synchronous language Esterel. The paper starts with a short introduction into Esterel and tackles available tools. The focus of this work is an examination of the design flow concerning the practical applicability, based on case studies and related work. Advantages and draw-backs of the design flow are discussed and compared to traditional hardware/software design flows.\",\"PeriodicalId\":133325,\"journal\":{\"name\":\"2009 IEEE International Symposium on Industrial Embedded Systems\",\"volume\":\"68 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-07-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE International Symposium on Industrial Embedded Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIES.2009.5196190\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE International Symposium on Industrial Embedded Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIES.2009.5196190","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Evaluation of an Esterel-based hardware/software co-design flow
This work describes the evaluation of a hardware/software co-design flow based on the synchronous language Esterel. The paper starts with a short introduction into Esterel and tackles available tools. The focus of this work is an examination of the design flow concerning the practical applicability, based on case studies and related work. Advantages and draw-backs of the design flow are discussed and compared to traditional hardware/software design flows.
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